CPU Port Contention Without SMT

CPU power management for SMT and CMP processors

Secretly Monopolizing the CPU Without Superuser Privileges

We describe a “cheat” attack, allowing an ordinary process to hijack any desirable percentage of the CPU cycles without requiring superuser/administrator privileges. Moreover, the nature of the attack is such that, at least in some systems, listing the active processes will erroneously show the cheating process as not using any CPU resources: the “missing” cycles would either be attributed to s...

Parallel Read Operations Without Memory Contention

We address the problem of organizing a set T of shared data into the memory modules of a Distributed Memory Machine (DMM) in order to minimize memory access connicts (i.e. memory contention) during read operations. Previous solutions for this problem can be found as fundamental subprocedures of the PRAM simulation methods on DMM presented during the last years. The eeciency of such solutions re...

Cpu Cpu 1 Cpu 2 Cpu

Coherent-cache shared-memory architectures often give disappointing performance which can be alleviated by manual tuning. We describe a new trace analysis tool, clarissa, which helps diagnose problems and pinpoint their causes. Unusually, clarissa works by analysing potential contention, instead of measuring predicted contention by simulating a speciic memory system design. This is important be...

[Single port distal pancreatectomy without spleen preserving].

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