CHIPS: Custom Hardware Instruction Processor Synthesis

Hardware / Software Partitioning for Custom Instruction

Implementation of Complex Division Custom Instruction Hardware on Nios-II Processor

As increasing the clock frequency leads to unmanageable heat and power dissipation the search is on for another way to get more power efficient and faster embedded systems. Given that chip area is also a constraint, we investigate the addition of a custom instruction to the processor instruction set which enables the execution of an efficient complex division. We have implemented software for c...

High Level Synthesis for Designing Custom Computing Hardware

We examine the application of High Level Synthesis to FPGA based computing systems. Our experience shows that high level synthesis allows for a level of design space exploration unrealizeable with register transfer level techniques. In addition, the use of high level tools allow designers to prototype their designs with high quality results and fast design turn around times. Our design ow makes...

Custom Instruction Generation for Configurable

This paper presents a novel framework to generating efficient custom instructions for common configurable processors with limited numbers of I/O ports in the register files and fixed-length instruction formats, such as RISCs. Unlike previous approaches which generate a single custom instruction from each subgraph, our approach generates a sequence of multiple custom instructions from each subgr...

The Propagated Instruction Processor

As the dimensions of electronic devices become smaller, they enter the realm of nano-electronics, where the device dimensions lie between the inter-atomic spacing (lnm) and the electron wavelength (lOnm). This offers greatly-enhanced packing density and speed of operation, but introduces the difficulty of maintaining signal quality over large distances. The paper introduces an architectural sol...