Booth-Encoded Karatsuba: A Novel Hardware-Efficient Multiplier

There is a recent boom being witnessed in emerging areas like IoMT (Internet of Medical Things), Artificial Intelligence for healthcare, and disaster management. These novel research frontiers are critical terms hardware cannot afford to compromise accuracy or reliability. Multiplier, one the most heavily used components, becomes crucial these applications. If optimized, multipliers can impact overall performance system. Thus, this paper, an attempt has been made determine potential accurate while meeting minimal requirements. In we propose Booth-Encoded Karatsuba multiplier provide its comparison with Wallace tree multiplier. architectures have developed using two types Booth encoding: Radix-4 Radix-8 16-bit, 32-bit 64-bit multiplications. The algorithm designed be parameterizable different bit widths, thereby offering higher flexibility. proposed mul- tiplier offers advantage enhanced significant reduction negligibly trad- ing off Power Delay Product (PDP). It observed that architecture increases increasing size due slight increase PDP. All implemented Verilog HDL Xilinx Vivado Design Suite.