Area Optimization Techniques for High-Density Spin-Orbit Torque MRAMs

This paper presents area optimization techniques for high-density spin-orbit torque magnetic random-access memories (SOT-MRAMs). Although SOT-MRAM has many desirable features of nonvolatility, high reliability and low write energy, it poses challenges to memory implementation because the use two access transistors per cell. We first analyze layout conventional bit-cell that includes vertical metal lines, a bit-line source-line, limiting horizontal dimension. further propose design reduce dimension by decreasing number lines cell without any performance overhead. Based on fact adjacent columns in bit-interleaved array are not simultaneously accessed, proposed share single source-line between consecutive bit-cells same row. The simulation result shows can achieve reduction 10–25% compared SOT-MRAM. comparison our designs with standard spin-transfer MRAM 45% lower 84% read 2.3 × higher read-disturb margin.