Architectures and Arithmetic for Low Static Power Consumption in Nanoscale CMOS
نویسندگان
چکیده
منابع مشابه
Power Consumption Analysis in CMOS Static Gates
This paper addresses power consumption in CMOS logic gates through an study considering the design and technology points-of-view. Through SPICE simulations, the relationship between charge/discharge and short-circuit components of dynamic power consumption are investigated both considering different logic gates and its evolution through technology scaling. Experimental results show that dynamic...
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ژورنال
عنوان ژورنال: VLSI Design
سال: 2009
ISSN: 1065-514X,1563-5171
DOI: 10.1155/2009/749272