An FPGA Implementation of-Regular Low-Density Parity-Check Code Decoder
نویسندگان
چکیده
منابع مشابه
An FPGA Implementation of (3, 6)-Regular Low-Density Parity-Check Code Decoder
Because of their excellent error-correcting performance, low-density parity-check (LDPC) codes have recently attracted a lot of attention. In this paper, we are interested in the practical LDPC code decoder hardware implementations. The direct fully parallel decoder implementation usually incurs too high hardware complexity for many real applications, thus partly parallel decoder design approac...
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ژورنال
عنوان ژورنال: EURASIP Journal on Advances in Signal Processing
سال: 2003
ISSN: 1687-6180
DOI: 10.1155/s1110865703212105