An Accurate Process-Induced Variability-Aware Compact Model-Based Circuit Performance Estimation for Design-Technology Co-Optimization
نویسندگان
چکیده
In sub-10nm FinFETs, Line-edge-roughness (LER) and metal-gate granularity (MGG) are the two most dominant sources of variability mostly modeled semi-empirically. this work, compact models LER MGG used. We show an accurate process-induced (PIV) aware model-based circuit performance estimation for Design-Technology Co-optimization (DTCO). This work is carried out using experimentally validated BSIM-CMG model on a 7nm FinFET node. First, we have shown bench-marking with state-of-the-art {\textbackslash}4x({\textbackslash}2.3x) accuracy improvement NMOS(PMOS) in device figure merits (DFoMs). Second, RO SRAM circuits variability. Further, {\textbackslash}22\% more optimistic estimate ({\sigma}/{\mu})\textsubscript{SHM} (Static Hold Margin) compared to V\textsubscript{DD} variation shown. Finally, demonstrate our improved DFoMs translated (CFoMs) estimation. For worst-case SHM (3({\sigma}/{\mu})\textsubscript{SHM}@VDD=0.75 V) state-of-the-art, dynamic(standby) power reduction by {\textbackslash}73\%({\textbackslash}61\%) Thus, enhanced enables credible DTCO significantly better estimates.
منابع مشابه
An Optimization-Based Approach for Analog Circuit Design
An efficient approach to optimize the performance of integrated analog circuits is described. The main objectives are to speed up the design process and obtain better, possibly optimal, performance compared to manual simulation-based device sizing schemes. The automatic generation of the cost function requires only a circuit netlist, a performance specification, and process parameters supplied ...
متن کاملAn Equation-based Optimization Approach for Analog Circuit Design
An efficient approach and an associated tool to optimize the performance of integrated analog circuits is described. The main objectives with the approach are to significantly speed up the design process and to obtain better overall, possibly optimal, circuit performance compared to a manual, simulation-based, approach. In order to achieve good agreement with circuit simulators high accuracy tr...
متن کاملA Circuit Technique for Variability- Aware Design of an Sram Cell
The primary motivation behind aggressive device scaling is to achieve improved performance and increased integration. These improvements come at the cost of increased sensitivity to PVT variations and standby leakage, particularly in area-constrained circuit such as SRAM that employs minimum-geometry devices. An attempt is made in this work to mitigate these problems in traditional 6T SRAM cell...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: IEEE Transactions on Electron Devices
سال: 2022
ISSN: ['0018-9383', '1557-9646']
DOI: https://doi.org/10.1109/ted.2021.3131966