A Wide-Range Four-Phase All-Digital DLL with De-Skew Circuit

A four-phase all-digital delay-locked loop (ADDLL) with a de-skew circuit for NAND Flash high-speed interfaces is proposed. The proposed adopts fall-edge-judgment phase adjuster and three-stage digitally controlled delay line to align the system input clock 0∘ output of DLL over wide frequency range, thus solving offset caused by skew. parallel-cascade configuration solve variable alignment problem mode switching, effectively improving phase-locked accuracy. fabricated in 0.13 μm CMOS process 0.072 mm2 core area. chip testing results show an operating range from 26 MHz 1.55 GHz typical error approximately 17 ps.