A Timing Yield Model for SRAM Cells at Sub/Near-Threshold Voltages Based on a Compact Drain Current Model

Sub/near-threshold static random-access memory (SRAM) design is crucial for addressing the bottleneck in power-constrained applications. However, high integration density and reliability under process variations demand an accurate estimation of extremely small failure probabilities. To capture such a “rare event” circuits, time storage overhead conventional simulations based on Monte Carlo (MC) analysis cannot be tolerated. On other hand, classic analytical methods predicting probabilities from physical expression become inaccurate sub/near-threshold voltage domain due to hypothetical distribution or oversimplified drain current ( $I_{ds}$ ) model nanoscale devices. This work first proposes simple but efficient empirical describe drain-induced barrier lowering (DIBL) effect. Based that, probability functions interest metrics SRAM are derived. Two models then put forward evaluate dynamic stabilities, including access write failure. The proposed can extended easily different types with read/write-assist circuits. validated against MC across operating voltages temperatures. average relative errors at 0.5-V notation="LaTeX">$V_{\mathrm{ DD}}$ only 8.8% access-time 10.4% model. size required sample data set notation="LaTeX">$43.6\times $ smaller than that state-of-the-art method.