A Test Vector Reordering for Switching Activity Reduction During Test Operation Considering Fanout
نویسندگان
چکیده
منابع مشابه
Reordering of Test Vector Using Artificial Intelligence Approach for Power Reduction during VLSI Testing
Optimization of testing power is a major significant task to be carried out in digital circuit design. Low power VLSI circuits dissipate more power during testing when compared with that of normal operation. As the feature size is scaled down with process technology advancement, power minimization has become a serious problem for the designers as well as the test engineers. Test vector reorderi...
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ژورنال
عنوان ژورنال: The Transactions of The Korean Institute of Electrical Engineers
سال: 2011
ISSN: 1975-8359
DOI: 10.5370/kiee.2011.60.5.1043