A Novel LDMOS with Ultralow Specific on-Resistance and Improved Switching Performance

A stepped split triple-gate SOI LDMOS with P/N strip (P/N SSTG LDMOS) is proposed, which has ultralow specific on-resistance (Ron,sp) and low switching losses. The proposed device a (TG) gates (SSGs). P strip, N-drift oxide trench are alternately arranged in the Z direction. Meanwhile, SSGs located of region distributed steps. Firstly, TG increases channel width (Wch) effect modulating current distribution, resulting lower Ron,sp higher transconductance (gm). Secondly, serve as field plate to assist depletion region, increasing optimal doping concentration (Nd-opt) further reducing Ron,sp. Moreover, also have electric distribution maintain high breakdown voltage (BV). gate-drain charge (QGD) losses reduced on account introduction SSGs. Thirdly, off-state, multidimensional assisted greatly Nd-opt. highly doped provides low-resistance path for current, reduces Compared almost equal voltage, QGD by 62% 63%, respectively.