A low supply voltage sensitivity low power oscillator design

With the rapid development of social economy, integrated circuit industry has developed rapidly. At same time, people’s requirements for cost, power consumption, integration, stability and other aspects chips have increased. Oscillators, as an important module providing clocks to chips, higher on-chip oscillators. The purpose this paper is achieve a low supply voltage sensitive oscillator. Based on research purpose, proposes adjustment oscillator flip level technique, which realizes that clock signal duty cycle 50% under typical case 4 V. center frequency 512 KHz, process angle trimming range capacitor trim 52.37%-211.28%. 2.5 V 5.5 V, variation 0.299%/V, sensitivity, consumes only 400 nA with dissipation.