A Low-Overhead Reconfigurable RISC-V Quad-Core Processor Architecture for Fault-Tolerant Applications
نویسندگان
چکیده
Radiation can affect the correct behavior of an electronic device. Hence, microprocessors used for space missions need to be protected against fault. TMR (Triple modular redundancy) is mitigating various kinds faults in circuit. Although provides excellent level reliability, it takes a large area and suffers from high power consumption. To reduce overheads DMR (double used. The approach significantly reduces resource overhead but also performance by imposing timing penalty. Various methods have been proposed since incarnation DMR, still challenging issue. this work, new based reconfigurable quad-core RV32IM processor architecture fault-tolerant applications. Depending upon environment operation application sensitivity, designed reconfigured work either normal mode or mode. novelty that feature makes energy-efficient optimally using all four cores provide results. computing Verilog HDL(Hardware Description Language) synthesized on 32nm CMOS (Complementary Metal-Oxide Semiconductor) process technology node Synopsys Design Compiler EDA (Electronic Automation) tool. Compared unprotected design, synthesis tool reports -21.75% reduction with time penalty +9.96% +17.89% approach. state-of-the-art system, design achieves -2.26% low its reliability intact as DMR. Further, prototyped tested FPGA (field-programmable gate array) fault-injection SEM (soft error mitigation) IP core.
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ژورنال
عنوان ژورنال: IEEE Access
سال: 2022
ISSN: ['2169-3536']
DOI: https://doi.org/10.1109/access.2022.3169495