A Gated Oscillator Clock and Data Recovery Circuit for Nanowatt Wake-Up and Data Receivers

This article presents a data-startable baseband logic featuring gated oscillator clock and data recovery (GO-CDR) circuit for nanowatt wake-up receivers (WuRxs). At each transition, the phase misalignment between coming from analog front-end (AFE) is cleared by GO-CDR circuit, thus allowing reception of long streams. Any free-running frequency mismatch GO bitrate does not limit number receivable bits, but only maximum equal consecutive bits (Nm). To overcome this limitation, proposed system includes calibration which reduces to ±0.5%, enabling WuRx be used with different encoding techniques up Nm = 100. A full prototype, including an always-on clockless AFE operating in subthreshold, was fabricated STMicroelectronics 90 nm BCD technology. The supplied 0.6 V, power consumption, excluding 12.8 nW during rest state 17 at 1 kbps rate. With On-Off Keying (OOK) modulated input −35 dBm RF after matching network (IMN), 10−3 missed detection rate 0 bit error tolerance measured, transmitting 63 packets ranging 63. total sensitivity, estimated IMN gain 100 MHz 433 MHz, −59.8 −52.3 dBm, respectively. In comparison ideal CDR, degradation sensitivity due 1.25 dBm. False alarm measurements lasting 24 h revealed zero overall false wake-ups.