A congestion-aware hybrid SRAM and STT-RAM buffer design for network-on-chip router

Network-on-chip (NoC) offers a scalable and flexible communication infrastructure for many-cores systems. Buffers in router is used fine-grain flow control Quality of Service (QoS), yet it the major contributor area power consumption. In this paper, we propose hybrid buffer design with SRAM Spin-Torque Transfer Magnetic RAM (STT-RAM) NoC leveraging novel architecture combined Virtual Channel (VC) Output Queuing (VOQ) to store congested uncongested separately. Experiments demonstrates that proposed scheme can achieve 11.8% network performance improvement 32.9% saving only 8.2% overhead degradation compared conventional based design.