A Comparison of Bit Serial and Bit Parallel DCT Designs
نویسندگان
چکیده
منابع مشابه
A Low-complexity Bit-serial Dct/idct Architecure
The implementation of the discrete cosine transform (DCT) for high transformation rates with data-flow architectures has been studied extensively, as well as its implementation for low rates on special purpose processors. With currently known solutions a problem arises if the application requires medium range speed, high accuracy, low latency, and low complexity. The novel bit-serial data-flow ...
متن کاملA Bit-serial Architecture for 1-d Multiplierless Dct
The Discrete Cosine Transform (DCT) is significantly of interest in the area of image compression according to its high compaction energy. It has become the core of many international standards such as JPEG, H.26x and the MPEG family [1-3]. In both software and hardware implementations, there appear many fast algorithms to speed up the computation of DCT. A 2-D DCT can be easily computed by rec...
متن کاملBit Serial Architecture for the Two-Dimensional DCT
We present an architecture for the calculation of the Two Dimensional Discrete Cosine Transform and its Inverse that admits a high data rate. It is based on the row-column decomposition, the use of a fast algorithm, serial digit arithmetic and redundant coding. The critical path is set by the delay of a multiplexer plus a binary adder with as many digits as the width of the serial digits to be ...
متن کاملSwitching Activity in Bit-Serial Constant-Coefficient Serial/Parallel Multipliers
Bit-serial architectures have the advantage of high throughput, area efficient multipliers. These multipliers are implemented using shift-add operations [1], with full adders and D flip-flops as building blocks. Multiplication with a constant fixed-point coefficient is commonly used in digital signal processing (DSP) circuits, such as digital filters [2][3]. The design of a constant-coefficient...
متن کاملA Bit-Serial Word-Parallel Finite Field Multiplier
A high speed bit-serial word-parallel finite field multiplier using redundant basis is proposed. It has been shown that the proposed architecture has higher speed compared to the previously proposed hybrid architectures using the same basis while having moderate complexity. The hybrid architecture of the proposed design provides designer the ability to set the trade off between area and delay d...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: VLSI Design
سال: 1995
ISSN: 1065-514X,1563-5171
DOI: 10.1155/1995/30583