A 6-Bit 20 GS/s Time-Interleaved Two-Step Flash ADC in 40 nm CMOS

A 6-bit 20 GS/s 16-channel time-interleaved (TI) analog-to-digital converter (ADC) using a two-step flash ADC with sample-and-hold (S/H) sharing technique and gain-boosted voltage-to-time (VTC) is presented for high-speed wireline communication systems. By one S/H between coarse fine stages in the ADC, input bandwidth as well area power efficiency can be improved without gain error ADCs. Thanks to an eight-time interpolation VTC, has small gate capacitance speed penalty, even voltage range. prototype implemented 40 nm CMOS process occupies 0.1 mm2 active area. The measured differential non-linearity (DNL) integral (INL) after offset calibrations were 0.45 0.39 least significant bit (LSB), respectively. With 9.042 GHz input, signal-to-noise distortion ratio (SNDR) spurious-free dynamic range (SFDR) 30.12 40.23 dB, of sub-ADC enables power-efficient track-and-hold amplifier (THA), resulting consumption 56.2 mW under supply 0.9 V. achieves figure merit (FoM) 107.4 fJ/conversion-step at GS/s.