A 5-bit 5 Gs/s flash ADC using multiplexer-based decoder

A 5-bit 4.2-GS/s flash ADC in 0.13-μm CMOS

This paper investigates and analyzes the resistive averaging network and interpolation technique to estimate the power consumption of preamplifier arrays in a flash analog-to-digital converter (ADC). By comparing the relative power consumption of various configurations, flash ADC designers can select the most power efficient architecture when the operation speed and resolution of a flash ADC ar...

A sub-mW pulse-based 5-bit flash ADC with a time-domain fully-digital reference ladder

The concept of time-domain reference-ladder for the implementation of fully-digital flash-ADCs is proposed in this work. The complete reference ladder is implemented using only digital circuits. Based on this concept, a flash ADC is proposed and implemented in this work using digital circuits, one comparator and a customized sample-and-ramp circuit. An unconventional time-to-digital conversion ...

Low Power Encoder and Comparator Design of 5-bit Flash Adc

2, 4 Bit Flash Adc Using Tiq Comparator

With the advancement of technology, data converters are widely used in modern communication and digital signal processing. ADCs are basic building blocks in many applications including storage systems, optical communication, radar communication, instrumentation and high-speed serial data links[1]. Different categories of ADC architectures are available based on their speed, resolution and power...

A 6-bit, 1-GHz Flash ADC in 0.35μm CMOS

+ Katholieke Universiteit Leuven, Kasteelpark Arenberg 10, B-3001 Heverlee, [email protected] . Abstract The design plan and measurement results of a very high-speed 6 bit CMOS Flash ADC converter are presented. The very high acquisition speed is obtained by improved comparator design. At these high frequencies power-efficient error correction logic is necessary. Measurements show th...