A 24 ?GHz PLL with low phase noise for 60 ?GHz Sliding-IF transceiver in a 65-nm CMOS

This work presents a 24 ?GHz integrated Phase-Locked Loop in 60 sliding-IF transceiver for IEEE 802.15.3c standard with low phase noise. For noise, varactor and MOM cap combination method is applied this PLL. The capacitor bank optimized to decrease the noise folding from circuit within method. analog PLL fabricated 65 ?nm CMOS technology of ?98.8 dBc/[email protected] ?MHz, reference spur ?62.4 dBc. power consumption 45.6 ?mW, including output buffer.