A 12-bit Low-input Capacitance SAR ADC with a Rail-to-Rail Comparator

The input capacitance of the SAR ADC is considered as a drawback in many applications. In this paper, 12-bit low-power with low-input based on separated DAC and sample-and-hold blocks (SB) structure proposed. SB suffers from variation common-mode voltage comparator causing nonlinear input-referred offset kickback noise. Here, closed loop rail-to-rail cancellation technique for body tuning order to stabilize structure, open gain controlled by adapting preamplifier. Using kept lower than 110 μV overall power 1 pJ/Conv. Complementary-clocked dynamic branches are exploited at decrease dependent noise error less LSB. bootstrapped switch’s controlling signal also modified achieve LSB 18.9% consumption. proposed designed standard 180 nm CMOS technology 1.8 V supply shrinking 2 pF, which leads 41 nW consumption supply. Electrical simulations including PVT, Monte-Carlo, post-layout parasitic extraction were run ensure effectiveness approach. features an ENOB 11.1-bit sampling rate MHz 117.9 μW competitive state-of-the-art, demonstrate virtue