250 MHz passive Q-modulator for reflection resonators

250 MHz Multiphase Delay Locked Loop for Low Power Applications

Received Mar 17, 2017 Revised Sep 8, 2017 Accepted Sep 20, 2017 Delay locked loop is a critical building block of high speed synchronous circuits. An improved architecture of amixed signaldelay locked loop (DLL) is presented here. In this DLL, delay cell based on single ended differential pair configuration is used for voltage controlled delay line (VCDL) implementation. This delay cell provide...

Characterization of Passive Fiber Resonators

A 50-MHz Multibit Sigma–Delta Modulator for 12-b 2-MHz A/D Conversion

Oversampling techniques offer several advantages for the implementation of high-resolution analog-to-digital (A/D) converters in VLSI technologies. This paper examines the application of oversampling techniques to A/D conversion at rates exceeding 1 MHz. A cascaded multibit sigma-delta (2A) modulator that substantially reduces the oversampling ratio required for 12-b conversion while avoiding s...

Design of a 70-MHz IF 10-MHz bandwidth bandpass ΣΔ modulator for WCDMA applications

In this paper we present a MASH bandpass Σ∆ modulator for WCDMA applications. The signal bandwidth of the proposed modulator is 10 MHz, centered around an intermediate frequency (IF) of 70 MHz. Each Σ∆ modulator of the MASH structure is based on a two-path architecture, which allow us to obtain the desired in-band noise shaping zeros and reduce the power consumption. The Σ∆ modulator is impleme...

70-MHz IF 10-MHz bandwidth bandpass $$\Upsigma\Updelta$$ modulator for WCDMA applications

A MASH bandpass RD modulator for wideband code division multiple access (WCDMA) applications is presented. The signal bandwidth of the proposed modulator is 10 MHz centered around an intermediate frequency (IF) of 70.5 MHz. Two two-path second-order bandpass RD modulators make the MASH architecture, which realizes a noise transfer function with four couples of complex conjugate zeros. The propo...