128-Bit Area Efficient Reconfigurable Carry Select Adder
نویسندگان
چکیده
منابع مشابه
128 Bit Low Power and Area Efficient Carry Select Adder
Carry Select Adder (CSLA) which provides one of the fastest adding performance. Traditional CSLA require large area and more power. Recently a new CSLA adder has been proposed which performs fast addition, while maintaining low power consumption and less area. This work mainly focuses on implementing the 128 bit low power and area efficient carry select adder using 0.18 μm CMOS technology. Base...
متن کاملHard ware implementation of area and power efficient Carry Select Adder using reconfigurable adder structures
In data processing processors, adder is a basic digital circuit. To perform any arithmetic operation, addition is the basic operation to perform. To compute fast arithmetic operations adder must be fastest. CSLA is the fastest adder when compare to RCA and CLA. From the structure of CSLA it is observed that there is a scope to reduce area further so that power can be lowered [3-4]. This paper p...
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Design of areaand power-efficient highspeed data path logic systems forms the largest areas of research in VLSI system design. In digital adders, the speed of addition is limited by the time required to transmit a carry through the adder. Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the...
متن کاملDesign of Area and Power Efficient Modified Carry Select Adder
Adders are one of the widely used digital components in digital integrated circuit design. The Carry Select Adder (CSA) provides a good compromise between cost and performance in carry propagation adder design. However, conventional CSA is still area-consuming due to the dual ripple carry adder (RCA) structure. In this paper, modification is done at gate-level to reduce area and power consumpti...
متن کاملEnergy and Area efficient Carry Select Adder on a reconfigurable hardware
Carry Select Adder (CSLA) is one of the high speed adders used in many computational systems to perform fast arithmetic operations. From the structure of the CSLA, it is clear that there is scope for reducing the gate count and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the logic resources and power of the CSLA. Based on ...
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ژورنال
عنوان ژورنال: International Journal on Cybernetics & Informatics
سال: 2016
ISSN: 2320-8430,2277-548X
DOI: 10.5121/ijci.2016.5438