Sub-threshold operation offers a compelling solution for ultra-low energy applications such as micro-sensors and embedded medical applications, where low energy needs are the primary concern instead of speed. By lowering the supply voltage below the transistors’ threshold voltage, we see a dramatic drop in energy consumption when compared to normal operations, but circuit instability and delay ...

--Neuromorphic systems have been primarily implemented using analog sub-threshold CMOS circuits primarily because the physics of subthreshold operation and biological signal processing are identical. The effects of attempting to model biology accurately, coupled with the slow dynamics of sub-threshold MOS circuits, have prevented these systems from capitalizing on the main benefit of silicon wh...

In this article, we proposed a Variable threshold MOSFET(VTMOS)approach which is realized from Dynamic Threshold MOSFET(DTMOS), suitable for sub-threshold digital circuit operation .Basically the principle of subthreshold logics is operating MOSFET in sub-threshold region and using the leakage current in that region for switching action, there by drastically decreasing power .To reduce the powe...

Motivated by emerging battery operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits, by operating the devices at low currents and low voltages[1,2,3,4].It is known that MOS devices and circuits especially CMOS circuits consume relatively low power[5,6] . But there seems to be a need t...

In recent times, dynamic supply voltage scaling (DVS) has been extensively employed to minimize the power and energy of VLSI systems. Also, sub-threshold circuits are becoming more popular. At the same time, the reliability of VLSI systems has become a major concern under Single Event Upsets (SEUs). SEUs are very problematic even for circuits operating at nominal voltages. With the increasing d...

In this article, we present ultralow leakage logic circuits by combining 3-D memristors with CMOS transistors. Significant current reductions of up to 99% are found experiments and simulation for a memristive hybrid-inverter if compared conventional inverter. Likewise, circuit simulations hybrid ring oscillators, NAND, or full adders show more than 100% gain in energy efficiency per cycle over ...

Digital circuits operating in the sub-threshold regime are able to perform minimum energy operation at a given delay. In the sub-threshold regime circuit delay, hence the leakage energy consumption depends on the supply voltage exponentially. By reducing the idle time of the circuit both the supply voltage that realizes minimum energy operation and the energy consumption can be reduced. This pa...

This work studies the effects of dynamic threshold design techniques on the speed and power of digital circuits. A new dynamic threshold transistor structure has been proposed to improve performances of digital circuits. The proposed switched-capacitor dynamic threshold PMOS (SC-DTPMOS) scheme employs a capacitor along with an NMOS switch in order to effectively reduce the threshold voltage of ...