A compact wideband 2 -6GHz highly linear low noise amplifier is designed for Digital RF application. This design is implemented using MMIC using GaAs pseudomorphic high electron mobility transistors (pHEMTs). The proposed design is fundamentally designed for SDR and cognitive radio application. This LNA is implemented in 0.5um GaAs process and has a gain of 30dB at 2.45GHz and 23dB at 5GHz,Nois...

A highly linear down conversion mixer with moderate gain used for 2.4GHz RF applications is presented in this paper using 0.18μm CMOS technology. The proposed mixer incorporates current bleeding technique & degenerative resistors to improve linearity and conversion gain. Also the negative feedback configuration of the circuit gives flat conversion gain increasing the overall bandwidth. The simu...

A CMOS low-noise amplifier (LNA) and mixer for a GPS front end is described. At 1.586Ghz the LNA minimum noise figure (NF) is 2.8dB, input third order intercept point (IIP3) is 2.45dB and forward gain is 30dB. With a 1.573Ghz local oscillator (LO) and a 1.586Ghz RF input the mixer minimum NF is 6.1dB, IIP3 is 12dB and a conversion gain of -3dB. The LNA and mixer consume 58mW of power from a 1.8...

This paper describes a 1.5-V 2.4-GHz silicon down conversion mixer with a CMOS gm Cell using 0.35 um process [1]. With a 2.3-GHz local oscillator (LO) and a 2.4-GHz RF input, the mixer minimum double sideband noise figure (DSB NF) is 8.9 dB. The input third-order intercept point (IIP3) is 0.5 dBm, and the power conversion gain is 18 dB.

The signals used in UMTS have wide bandwidth and high crest factors. Circuit designers use sinusoids to design and simulate their building blocks. Formulas are presented relating the various distortion effects of the W-CDMA signals like adjacent channel leakage ratio (ACLR), cross modulation or intermodulation to well-known linearity measures like input intercept point of third(IIP3) and second...

A low-noise amplifier (LNA) uses low-loss monolithic transformer feedback to neutralize the gate–drain overlap capacitance of a field-effect transistor (FET). A differential implementation in 0.18m CMOS technology, designed for 5-GHz wireless local-area networks (LANs), achieves a measured power gain of 14.2 dB, noise figure (NF, 50 ) of 0.9 dB, and third-order input intercept point (IIP3) of+0...

This paper presents a design of 2.4 GHz low noise amplifier (LNA) for wireless sensor network (WSN) applications using CMOS 0.13 μm Silterra process. The proposed LNA employs a self-biased inverter to obtain high gain and able to operate at low supply voltage. The simulation results indicated that the proposed LNA achieves an input return loss (S11) of -37.7 dB, output return loss (S22) of -28....

In this work, we present a design and simulation of low power consumption down conversion Gilbert-Cell mixer, in the 1.9 GHz wireless application. The circuit is in a 65 nm – CMOS technology at a supply voltage of 1.8 V. The obtained results show a third order input intercept point (IIP3) and a Noise Figure in the order of 1.7 dBm and 3.13 dB respectively, when the conversion gain equal to 13.9...

The LNA is implemented using 90nm CMOS technology. The cascode topology with single-ended source degeneration using inductor is employed. The high gain is achieved by using common-source (CS) amplifier. A different input matching as well as output matching topology may improve the efficiency and minimize noise of the LNA. An inductance network (Lg, Ls) is used for input matching. An interstage ...

We propose a design methodology of a low-voltage CMOS low-noise amplifier (LNA) consisting of a common-source and a common-gate stages. We first derive equations of power gain, noise figure (NF) and input third-order intercept point (IIP3) of the two-stage LNA. A design methodology of the LNA is presented by using graphs based on analytical equations. A 1-V 5.4-GHz LNA was implemented in 0.15-μ...