tac (time to amplitude convertor) is one of the most important time measurement instrumentswhich has great significance in many fields of science, especially radiation physics. a tac unit has beendesigned based on the start-stop analog method and nim (nuclear instrument modules) standards. afterdesigning the circuit, it was simulated by pspice software and constructed by discrete and integrated...

The Integral Non-Linearity (INL) is the most significant static parameter of Analog-to-Digital Converters. This paper presents a comparison between different INL test techniques based on INL estimation from the spectrum of the converted signal. Then, we investigate whether the most accurate technique is applicable in a realistic hardware configuration.

This paper presents a new BIST(Built-in Selftest) method for A/D converters. The method characterizes the static parameters of A/D converter like offset, gain, INL(Integral Non-linearity) and DNL(Differential Non-linearity). It uses a ramp signal as a test stimulus and consists of three detectors – a transition detector, an INL detector and a DNL detector. The transition detector checks the cod...

VLSI technology is to optimize the any type of digital architecture used to enhance the various applications. One of the mainobjectives is to reduce the glitch energy in various systems. The survey is to optimize glitch energy. Different techniques are used to improve the performance by reducing the glitch. Some of the parameters areSpurious Free Dynamic Range (SFDR), Along with Integral Non Li...

Conventionally, the integral non-linearity of an analogue to digital converter (ADC) is measured using a pure sine wave test signal [1]. The measured amplitude probability distribution function (APDF) of the ADC output is compared with the ideal distribution and the differences used to calculate integral non-linearity error (INL). Accuracy of this method is limited by the practical problem of g...

A CMOS 8-bit binary type current steering Digital to Analog Converter DAC with dynamic random return to zero technique to improve dynamic performance is presented in this paper. Current steering DAC has advantage of constant output impedance and high conversion rate. To demonstrate the proposed technique, 8 bit CMOS DAC is designed and layout is prepared in 90 nm technology. Computation of Inte...

Ab strac t – This paper deals with an innovative strategy to shorten the record size required to estimate the Integral Non-Linearity (INL) of Analog-to-Digital Converters (ADC's) through the so-called Sinewave Histogram Test (SHT). Such a size reduction is achieved by low-pass filtering the collected sequences of test samples using a simple moving average filter. After some preliminary simulati...

The histogram-based technique is commonly used for testing of Analog-to-Digital Converters (ADC). One of the parameters measured thanks to this technique is the Integral Non Linearity (INL). INL is also used as an initial data related to the ADC performances for the computation of a correction table in case of a LUT-based correction technique. In this context of embedded INL measurement and emb...

This paper proposes a reconfigurable current steering digital to analog converter (DAC). The differential non-linearity error (DNL) of the DAC is estimated on-chip. This is used to reconfigure the switching sequence to get a lower integral nonlinearity error (INL). A 10 bit segmented DAC along with the associated circuits for DNL estimation was designed and fabricated using 0.35μm CMOS technolo...

Abstract: The analysis of the effect of the parasitic capacitors of the split capacitor array on the successive approximation register analog-to-digital converter’s charachteristics is presented. The Verilog-A model of the split capacitor array is developed based on the analysis. The model takes the effects of parasitic capacitors into account, and the values of these parasitic capacitors can b...