this paper presents a new method to reduce consumption power in flash adc in 65nm cmos technology. this method indicates a considerable reduction in consumption power, by removing comparators memories. the simulations used a frequency of 1 ghz, resulting in decreased consumption power by approximately 90% for different processing corners. in addition, in this paper the proposed method was desig...

In this paper, a new design for a low power CMOS flash Analog-to-Digital Converter (ADC) is proposed. A 6-bit flash ADC, with a maximum acquisition speed of 1GHz, is implemented in a 1.2 V analog supply voltage. HSpice simulation results for the proposed flash ADC verifying the analytical results are also given. It shows that the proposed 6-bit flash ADC consumes less power i n a commercial 90n...

This paper presents the design and implementation of a 2.5V 12-hit high performance and low cost pipeline Analog-to-Digital converter (ADC) architecture using CMOS technology. A modified flash ADC was employed instead of the traditional flash ADC to implement the sub-ADC in the designed pipeline ADC scheme to reduce the device complexity and attain lower system power consumption. The designed p...

This paper introduces three popular analog-to-digital converter (ADC) architectures to readers: the flash ADC, the multi-step flash ADC, and the pipeline ADC. The fundamental operating principles of these three architectures are described. The specific topic of interest of this paper is methods of improving ADC accuracy. For the flash ADC, the concept of 2X interpolation to increase ADC resolut...

The analog-to-digital converter (ADC) is an essential part of system-on-chip (SoC) products because it bridges the gap between the analog physical world and the digital logical world. In the digital domain, low power and low voltage requirements are becoming more important issues as the channel length of MOSFET shrinks below 0.25 sub-micron values. Moreover, SoC trends force ADCs to be integrat...

This paper investigates and analyzes the resistive averaging network and interpolation technique to estimate the power consumption of preamplifier arrays in a flash analog-to-digital converter (ADC). By comparing the relative power consumption of various configurations, flash ADC designers can select the most power efficient architecture when the operation speed and resolution of a flash ADC ar...

Owing to its high complexity the hardware development of a flash ADC of larger wordlength has always been a challenging issue. Being the fastest ADC available in practice, flash ADCs are the only solution for digitizing fast signals demanded by on-line real time digital processors. As computer designers have launched 64-bit machines into use, for real time processing applications they need word...

The main focus of this paper is to design a “Low power Flash ADC” for ultra-wide band applications using CMOS 90nm technology. Flash ADC consists of a reference generator, array of comparators, 1-out-of N code generator, Fat tree encoder and output D latches. The demanding issues in the design of a low power flash ADC is the design of low power latched comparator. The proposed comparator in thi...

This research presents the review of Analog to Digital Convertor (ADC). For ADC there are mainly four different methods, Flash ADC, Pipelined ADC, Successive Approximation ADC, and Sigma Delta ADC. The Flash ADC is the Fast ADC. For Designing the ADC, the parameters important are Static and Dynamic. In static parameters Differential Non Linearity Error (DNLE), Integral Non Linearity Error (INLE...

A high-speed low-power flash analog-to-digital converter is designed and optimized in a 0.13μm CMOS technology. The ADC consumes 65mW with a supply voltage of 1.2V at 1.2G samples per second. Static DNL and INL are 0.1 LSB and 0.2LSB respectively. The figure of merit shows 1.3pJ per conversion step. The simulation result of the full flash ADC shows improvement in nonlinearity and power dissipat...