This tutorial paper reviews the state of knowledge of on-chip ESD (electrostatic discharging) protection circuit design for integrated circuits. The discussion covers critical issues in ESD design, such as, ESD test models, ESD failure mechanism, ESD protection structures, ESD device modeling, ESD simulation, ESD layout issues, and ESD influences on circuit functionality, etc. This review serve...

The application of Preventive Maintenance (PM) and Statistical Process Control (SPC) are important practices to achieve high product quality, small frequency of failures, and cost reduction in a production process. However there are some points that have not been explored in depth about its joint application. First, most SPC is performed with the X-bar control chart which does not fully conside...

Co-design strategy with low-capacitance (low-C) consideration for on-chip ESD protection in RF ICs is a solution to mitigate RF performance degradations caused by ESD protection device. A low-C design on ESD protection device was presented in this paper. An RF power amplifier (PA) codesigned with the low-C ESD protection device was also presented in this paper. Before ESD stress, RF performance...

ESD design of RFIC is a great issue due to the lack of ESD device models and the interactions between ESD protection and core circuits of RFIC. In this paper, a novel co-design methodology incorporating devicelevel simulation of ESD device and RF circuit design is proposed. In this methodology, the ESD protection is incorporated into RFIC core circuit design by extracting S parameters and const...

Acceptance control charts (ACC), as an effective tool for monitoring highly capable processes, establish control limits based on specification limits when the fluctuation of the process mean is permitted or inevitable. For designing these charts by minimizing economic costs subject to statistical constraints, an economic-statistical model is developed in this paper. However, the parameters of s...

polysilicon diodes to trigger ESD protection device is proposed to achieve excellent on-chip ESD protection. Design methodology of this novel ESD clamp circuit has been derived in detail. Some controlled factors in the novel ESD clamp circuit can be exactly calculated to design a suitable ESD clamp circuit for different power supply applications. By adding this efficient power-rail ESD clamp ci...

A substrate-triggered technique is proposed to improve electrostatic discharge (ESD) protection efficiency of ESD protection circuits without extra salicide blocking and ESD-implantation process modifications in a salicided shallow-trench-isolation CMOS process. By using the layout technique, the whole ESD protection circuit can be merged into a compact device structure to enhance the substrate...

Two new electrostatic discharge (ESD) protection design by using only 1 × VDD low-voltage devices for mixedvoltage I/O buffer with 3 × VDD input tolerance are proposed. Two different special high-voltage-tolerant ESD detection circuits are designed with substrate-triggered technique to improve ESD protection efficiency of ESD clamp device. These two ESD detection circuits with different design ...

The configurable electrostatic discharge (ESD) protection cells have been implemented in a commercial 65-nm CMOS process for 60-GHz RF applications. The distributed ESD protection scheme was modified to be used in this work. With the consideration of parasitic capacitance from I/O pad, the ESD protection cells have reached the 50-X input/output matching to reduce the design complexity for RF ci...

control chart is the most well-known chart to monitor the number of nonconformities per inspection unit where each sample consists of constant size. generally, the design of a control chart requires determination of sample size, sampling interval, and control limits width. optimally selecting these parameters depends on several process parameters, which have been considered from statistical and...