in this paper, a high speed delay-locked loop (dll) architecture ispresented which can be employed in high frequency applications. in order to design the new architecture, a new mixed structure is presented for phase detector (pd) and charge pump (cp) which canbe triggered by double edges of the input signals. in addition, the blind zone is removed due to the elimination of reset signal. theref...

We present an analytical frequency-domain phase noise model for fractional-N phase-locked loops (PLL). The model includes the noise of the crystal reference, the reference input buffer, the voltage-controlled oscillator (VCO), the loop filter, charge pump device noise, sigma-delta modulator (SDM) noise including its effect on the in-band phase noise. Thermal device noise of the charge pump and ...

An improved charge pump (CP) for phase locked loop (PLL) applications is presented. The proposed charge pump circuitry employs a variable current source in its sink path, which realizes feedback network for calibration. This scheme of charge pump minimizes mismatch between the sourcing current and the sinking current efficiently. The circuit is simulated in 0.18um CMOS technology and the simula...

The charge pump (CP) circuit is a key element in a phaselocked loop (PLL). Its function is to transform the Up and Down signals from the phase/frequency detector into current. In CMOS CPs, which have Up and Down switches made of p-channel MOS and n-channel MOS, respectively, a current mismatch occurs when dumping the charge to the loop filter. This current mismatch of the CP in the PLL generate...

The charge-pump (CP) mismatch current is a dominant source of static phase error and reference spur in the nano-meter CMOS PLL implementations due to its worsened channel length modulation effect. This paper presents a charge-pump (CP) mismatch current reduction technique utilizing an adaptive body bias tuning of CP transistors and a zero CP mismatch current tracking PLL architecture for refere...

This paper presents a Low power phase frequency detector with charge pump for low power phase lock loop. The phase frequency detector with dead zone compensation has been proposed. The paper contains the detailed circuit diagram of PFD and charge pump with 1.8v power supply and 500MHz input frequency. The design has been realized using 0.18um CMOS technology. Keywords— Low Power, PLL, PFD, CP

We present a 500-MHz, ultra-low-power phase-locked loop (PLL) realized with the near-threshold supply voltage of 0.4 V in 65-nm CMOS technology. Our PLL employs a new charge pump (CP) circuit structure that can greatly reduce CP up/down current mismatch and their variation with voltage-controlled oscillator (VCO) control voltages. The PLL consumes only 127.8 μW, which corresponds to power effic...

CONDUCTION-MODE VOLTAGE SOURCE CHARGE-PUMP POWER FACTOR CORRECTION ELECTRONIC BALLAST * Ray-Lee Lin, Hsu-Ming Shih, National Cheng Kung University, Tainan, Taiwan Chen-Yao Liu, Kuo-Bin Liu, National Synchrotron Radiation Research Center, Hsinchu, Taiwan Abstract This paper presents the piezoelectric transformer (PT) based continuous-conduction-mode (CCM) voltage source (VS) charge-pump (CP) pow...

The designing of charge pump with high gain OpAmp is a challenging task for getting faithful response .Design of high performance phase locked loop require ,a design of high performance charge pump .We have designed a operational amplifier for reducing the error caused by high speed glitch in a transistor and mismatch currents . A separate Op-Amp has designed in 180 nm CMOS technology by CADENC...