Superior electronic properties of graphene make it a substitute candidate for beyond-CMOSnanoelectronics in electronic devices such as the field-effect transistors (FETs), tunnel barriers, andquantum dots. The armchair-edge graphene nanoribbons (AGNRs), which have semiconductor behavior,are used to design the digital circuits. This paper presents a new design of ternary half a...

The aim of this paper is to design Carbon Nanotube Field Effect Transistor-based (CNTFET-based) combinational circuits with improved Power Delay Product (PDP). Ternary logic circuits have attracted substantial interest due to their capability of increasing information content per unit area. As a result, the geometry-dependent threshold voltage of CNTFETs is effectively used to design a ternary ...

We introduce a new implementation of a ternary adder with four inputs and two outputs. This ternary adder reduces the number of digits in a multiplication compared with a binary multiplication. One advantage of the ternary adder is that four instead of three inputs within a binary representation will be summed up. In this paper we will compare the complexity of binary against ternary multiplier...

This paper presents a new approach for converting a ternary reversible circuit implemented from a truth table into an online testable circuit. Our approach adds three extra lines to the given circuit, inserts Feynman gates and M-S gates, and replaces the ternary Toffoli gates (KP-m gates) with TKP-(m+1) gates. Our approach works with only 2×2 gates and 1×1 gates and covers a higher number of de...

A new proposal is given to design a spin half-adder in nano-junction. It well known that at finite voltage net circulating current (known as circular current) appears within mesoscopic ring under asymmetric ring-to-electrode interface configuration. This induces magnetic field the center of ring. We utilize this phenomenon construct half adder. The induced used regulate alignments local free sp...

Compressor trees are efficient circuits to realize multi-operand addition with fast carry-save arithmetic. They can be found in various arithmetic applications like multiplication, squaring and the evaluation of polynomials with application to function approximation. Finding good elementary compressing elements on FPGAs is a non-trivial task as an efficient mapping to look-up tables and carry-c...

This paper presents a ternary half adder and 1-trit multiplier using carbon nanotube transistors. The proposed circuits are designed pass transistor logic dynamic logic. Ternary uses less connections than binary logic, voltage changes required for the same amount of data transmission. Carbon transistors have advantages over MOSFETs, such as mobility electrons holes, ability to adjust threshold ...

Abstract Except for qubits which the different possible values are unordered, of m -valued circuits either with voltage levels, current levels or charge totally ordered. Either at Math level (Post algebras) circuit level, it means that each multiple valued must be decomposed into binary processed computation and finally converted a level. Using ternary adders as example, we show ternary-to-bina...

We consider an original ternary number system called the ternary mirror-symmetrical number system in the article. It is a synthesis of the classical ternary symmetrical number system and the number system with an irrational base called Bergman’s number system. The main engineering result is a development of an original matrix and pipeline ternary mirror-symmetrical adder, which can be used for ...

Implementation of a linear optics quantum multibit half-adder that could show potential scalability is discussed. Parametric down-conversion sources are assumed that are pumped by a mode carrying orbital angular momentum l. A single photon from a pair is prepared by detection of its twin. This preparation of a single photon defines two bits to be summed and the starting carry control bit. This ...