Static power dissipation is increases with the scaling in threshold voltage and expected to become important part of total power consumption. In the present work, a new configuration of level shifters for low power application in 0.25μm technology has been presented. The proposed circuits utilize the merit of stacking technique by which there is reduction in leakage power. In this work a new le...

Power consumption is an increasingly important issue in general purpose processors, particularly in the mobile computing segment. In present processors, most of the power dissipation is dynamic power dissipation, which arises due to signal transitions. Various techniques have been studied and implemented to reduce dynamic power dissipation, including clock gating, cache sub-banking, voltage sca...

This paper introduces a peculiar approach of designing Static Random Access Memory (SRAM) memory cell in Quantum-dot Cellular Automata (QCA) technique. The proposed design consists of one 3-input MG, one 5-input MG in addition to a (2×1) Multiplexer block utilizing the loop-based approach. The simulation results reveals the excellence of the proposed design. The proposed SRAM cell achieves 16% ...

A method to reduce the power dissipated by PLAs is presented in [3]. This method is addressing both static and dynamic PLAs. The objective is to minimize the number of literals and product terms of a logic function. However, [3] concluded that the static power dissipation of the NOR gates is the dominant power dissipation, and the optimization proposed cannot decrease significantly the power di...

In this paper, we discuss a design technique to reduce the power dissipation of CML buffers for on-chip transmissionlines. CML buffers can operate in higher frequency than conventional static CMOS buffers. On the other hand, the power dissipation is larger than that of the static CMOS buffers. We reduce the power dissipation by using an impedance-unmatched driver. From the pole frequency analys...

Due to miniaturization of circuits mobility degradation, velocity saturation and power dissipation issues are critical in the design of VLSI circuits. In this paper various techniques to minimize power dissipation due to glitches are discussed. Total power consumption consists of two major parts like static power consumption and dynamic power consumption. In the total power, the static power is...

P ower dissipation has evolved into an instrumental design optimization objective due to the growing demand for portable electronics equipment as well as due to excessive heat generation in high-performance systems. In the former case , low-power techniques are employed to prolong battery life, while in the latter case, low-power techniques are required to mitigate the reliability problems that...

Excessive switching activity during scan testing can cause average power dissipation and peak power during test to be much higher than during normal operation. This can cause problems both with heat dissipation and with current spikes. Compacting scan vectors greatly increases the power dissipation for the vectors (generally the power becomes several times greater). The compacted scan vectors o...

Static power consumption is nowadays a crucial design parameter in digital circuits due to emergent mobile products. Leakage currents, the main responsible for static power dissipation during idle mode, are increasing dramatically in sub-100nm processes. Subthershold leakage rises due to threshold voltage scaling while gate leakage current increases due to scaling of oxide thickness. It means t...

The study of the power dissipation sources of CMOS circuits is presented. Specifically, the main principles of dynamic, short-circuit, static, and leakage power dissipation are illustrated together with the low power strategies for reducing each power component. Furthermore, we enlighten to some innovative techniques of power reduction, which are based on multiple supply voltages and multiple t...