SRAM is designed to provide an interface with CPU and to replace DRAMs in systems that require very low power consumption. Low power SRAM design is crucial since it takes a large fraction of total power and die area in high performance processors. A SRAM cell must meet the requirements for the operation in submicron/nano ranges. 8T SRAM is traditionally concerned as a more reliable memory cell,...

This paper proposes a low power SRAM based on five transistor SRAM cell. Proposed SRAM uses novel word-line decoding such that, during read/write operation, only selected cell connected to bit-line whereas, in conventional SRAM (CV-SRAM), all cells in selected row connected to their bit-lines, which in turn develops differential voltages across all bit-lines, and this makes energy consumption o...

This paper proposes a low power SRAM based on five transistor SRAM cell. Proposed SRAM uses novel word-line decoding such that, during read/write operation, only selected cell connected to bit-line whereas, in conventional SRAM (CV-SRAM), all cells in selected row connected to their bit-lines, which in turn develops differential voltages across all bit-lines, and this makes energy consumption o...

As we shrink down devices with technology scaling, process variation increases and it hinders SRAM VMIN scaling. Using peripheral assists, we can further lower the VMIN at the cost of energy and area. However, the SRAM VMIN varies with voltage, temperature and operating frequency variations, and it is hard to determine in real time. Prior work shows theoretically that canary SRAMs using reverse...

As process technology is scaled down, a large-capacity SRAM will be used. Its power must be lowered. The V th variation of the deep-submicron process affects the SRAM operation and its power. This paper compares the macro area, readout power, and operating frequency among dual-port SRAMs: an 8T SRAM, 10T single-end SRAM, and 10T differential SRAM considering the multi-media applications. The 8T...

Power Stringent Static Random Access Memory (SRAM) design is very much essential in embedded systems such as biomedical implants, automotive electronics and energy harvesting devices in which battery life, input power and execution delay are of main concern. With reduced supply voltage, SRAM cell design will go through severe stability issues. In this paper, we present a highly stable average n...

In this paper the gate leakage current analysis of the Conventional 6T SRAM, NC-SRAM, PP SRAM, and P3 SRAM cell has been carried out. It has been observed that due to pMOS stacking and direct supply body biasing in the P3 SRAM Cell, there is a reduction of gate leakage current 66.55%, 34.42%, and 90.99% with respect to the 6T, NC-Cell, and PP cell, respectively for VDD=0.8V. For VDD=0.7V, it is...

In this paper, we have proposed the concept of 7Transistor SRAM. 7-Transistor SRAM has been designed to provide an interface with CPU and to replace DRAM in systems that require very low power consumption. The feature of 7Transistor SRAM like low power consumption and leakage current have been analyzed with 45nm technology. The comparative study and mathematical modeling have been proposed for ...

High-density and high-performance single-port and dual-port SRAM increasingly occupy a majority of the chip area in System-on-Chip product designs. Therefore, good yieldability and manufacturability of the SRAM are essential. At the same time there is tremendous competitive pressure to get the best SRAM density and performance. We have previously published and presented the industry’s smallest ...