In this work, a novel Silicon on Insulator (SOI) MOSFET is proposed and investigated. The drain and source electrode structures are optimized to enhance ON-current while global device temperature and hot carrier injection are decreased. In addition, to create an effective heat passage from channel to outside of the device, a silicon region has embedded in the buried oxide. In order to reduce th...

Silicon-on-insulator (SOI) CMOS offers a 20–35% performance gain over bulk CMOS. High-performance microprocessors using SOI CMOS have been commercially available since 1998. As the technology moves to the 0.13m generation, SOI is being used by more companies, and its application is spreading to lower-end microprocessors and SRAMs. In this paper, after giving a short history of SOI in IBM, we de...

Silicon On Insulator (SOI) can leverage a lot of new advantages for circuit designers compared to conventional bulk technology. In particular, the improved S-factor and reduced junction capacitance make it very appealing for next generation low power, high performance DRAM systems. However, the benefits of the SOI technology do not come entirely for free. In this project, we characterized the k...

This letter investigates hot-carrier-induced degradation on 0.1 m partially depleted silicon-on-insulator (SOI) nMOSFETs at various ambient temperatures. The thermal impact on device degradation was investigated with respect to body-contact nMOSFETs (BC-SOI) and floating-body SOI nMOSFETs (FB-SOI). Experimental results show that hot-carrier-induced degradation on drive capacity of FB-SOI device...

Abstarct The work presents the newly deploying technology in semiconductor industry called silicon on insulator (SOI). Its two technology partially and fully depleted SOI and describe how these are different from conventional bulk MOS technology, advantages over bulk technology and floating body effect of PD/FD SOI technology, factors effecting floating body such as kink effects in PD SOI, para...

This paper analyze the soft error tolerance related to layout structures on 65-nm bulk and SOI processes. The layout structure in which well contacts are placed between redundant latches suppresses MCU effectively. Also the tolerance of SOI structure transistor is estimated by TCAD simulations. The charge collection mechanism is suppressed by the BOX (Buried Oxide) in SOI transistor. Charge sha...

This paper introduces a novel silicon-on-insulator (SOI) metal–semiconductor field-effect transistor (MESFET) with an implanted N layer (INL-SOI MESFET) to improve the DC and radio frequency characteristics. The DC and radio frequency characteristics of the proposed structure are analyzed by the 2-D ATLAS simulator and compared with a conventional SOI MESFET (C-SOI MESFET). The simulated result...

The fully-depleted SOI-MOSFET model HiSIM-SOI for circuit simulation is the first model for circuit simulation based on a complete surface-potential description. HiSIM-SOI solves the surface potentials at all three SOI-surfaces perpendicular to the channel surface self-consistently. Besides verification against measured I-V characteristics, HiSIM-SOI is also verified with a 1/f noise analysis, ...

Hot-carrier-induced degradation of partially depleted SOI CMOSFETs was investigated with respect to body-contact (BC-SOI) and floating-body (FB-SOI) for channel lengths ranging from 0.25 down to 0.1 m with 2 nm gate oxide. It is found that the valence-band electron tunneling is the main factor of device degradation for the SOI CMOSFET. In the FB-SOI nMOSFET, both the floating body effect (FBE) ...