A novel and robust scheme for radix-4 Booth scheme implemented in Carbon Nanotube Field-Effect Transistor (CNTFET) technology has been presented in this paper. The main advantage of the proposed scheme is its improved speed performance compared with previous designs. With the help of modifications applied to the encoder section using Pass Transistor Logic (PTL), the corresponding capacitances o...

This paper describes optimized radix-4 booth multiplier algorithm for multiplication of two binary numbers on VHDL device. Radix-4 Booth’s algorithm is presented as an alternate solution of basic binary multiplication, which can help in reducing the number of partial products by a factor of 2. Radix-4 Booth’s multiplier alters the way of addition of partial products thereby using Carry-Save-Add...

In this paper we propose a modified probabilistic estimation bias (PEB) formula for fixed-width radix-4 Booth multiplier. The modified PEB formula estimates the same compensation value as the existing PEB formula without rounding operation. A bias circuit based on modified PEB formula generates one less carry-bit and involves less logic resources than the existing PEB circuit. The partial produ...

This paper Describes implementation of radix-2 Booth Multiplier and this implementation is compared with Radix-4 Encoder Booth Multiplier. This Implementation describes in the Form of RTL Schematic and Comparison is also done by using RTL Schematic. A Conventional Booth Multiplier consists of the Booth Encoder, the partial-product tree and carry propagate adder [2, 3]. Different schemes are add...

Approximate computing is an attractive design methodology to achieve low power, high performance (low delay) and reduced circuit complexity by relaxing the requirement of accuracy. In this paper, approximate Booth multipliers are designed based on approximate radix-4 modified Booth encoding (MBE) algorithms and a regular partial product array that employs an approximate Wallace tree. Two approx...

The multiplication operation is present in many parts of a digital system or digital computer, most notably in signal processing, graphics and scientific computation. With advances in technology, various techniques have been proposed to design multipliers, which offer high speed, low power consumption and lesser area. Thus making them suitable for various high speeds, low power compact VLSI imp...

This paper proposes two parallelized radix-4 scalable Montgomery multiplier implementations. The designs do not require precomputed hard multiples of the operands, but instead uses Booth encoding to compute products. The designs use a novel method for propagating the sign bits for negative partial products. The first design right shifts operands to reduce critical path length when using Booth e...

In this paper, we present a novel high-speed lowcomplexity four data-path 128-point radix-2 FFT/IFFT processor for high-throughput MB-OFDM UWB systems. The high radix radix-2 multi-path delay feed-back (MDF) FFT architecture provides a higher throughput rate and low hardware complexity by using a four-parallel data-path scheme. A method for compensating the truncation error of fixed-width Booth...

The residue number system is widely used in applications such as communication systems, cryptography, digital filters, signal processors, fault-tolerant detection, and so on. This paper proposes a multifunction modulo (2n ± 1) multiplier based on the radix-4 Booth encoding scheme that can operate both − + multipliers using same hardware structure with only one control signal. A novel proposed a...