this paper presents a modified 32-bit rom-based direct digital frequency synthesizer (ddfs). maximum output frequency of the ddfs is limited by the structure of the accumulator used in the ddfs architecture. the hierarchical pipeline accumulator (hpa) presented in this paper has less propagation delay time rather than the conventional structures. therefore, it results in both higher maximum ope...

This paper presents a modified 32-bit ROM-based Direct Digital Frequency Synthesizer (DDFS). Maximum output frequency of the DDFS is limited by the structure of the accumulator used in the DDFS architecture. The hierarchical pipeline accumulator (HPA) presented in this paper has less propagation delay time rather than the conventional structures. Therefore, it results in both higher maximum ope...

In this paper, an architecture of the RISC processor for pro-grammable logic controllers is proposed. Execution characteristics of relay ladder logic, the most common language of PLCs, are analyzed with various application programs. A conditional execution mechanism is developed to prevent pipeline hazards caused by the inherent execution behaviour of relay ladder logic. The instruction sets of...

This paper presents a merged multiplyaccumulate (MAC) hardware that is based on the modified Booth algorithm. The carry-save method is used in the Booth encoder, the Booth multiplier, and the accumulator sections to guarantee the fastest possible. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Also, the proposed ...

This paper presents a merged multiplyaccumulate (MAC) hardware that is based on the modified Booth algorithm. The carry-save method is used in the Booth encoder, the Booth multiplier, and the accumulator sections to guarantee the fastest possible. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Also, the proposed ...

Abstract Experimental regulating parameters of the non-stationary expansion air inside a bladder-type hydraulic accumulator, working with simple short pipeline, are presented in paper. The technique continuous online monitoring changes time volume and absolute pressure accumulator during discharge process has been improved. Three series experimental studies transient gas processes at different ...

This paper presents a merged multiplyaccumulate (MAC) hardware that is based on the modified Booth algorithm. The carry-save method is used in the Booth encoder, the Booth multiplier, and the accumulator sections to guarantee the fastest possible. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Also, the proposed ...

This paper presents a merged multiplyaccumulate (MAC) hardware that is based on the modified Booth algorithm. The carry-save method is used in the Booth encoder, the Booth multiplier, and the accumulator sections to guarantee the fastest possible. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Also, the proposed ...

AbstmctA bit-level pipelined 12 x 12-b two’s-complement multiplier with a 27-b accumulator has been designed and fabricated in a 1.0-pm p-well CMOS technology. A new “quasi N-P domino logic” structure has been adopted to increase the throughput rate, and special pipeline structures were used in the accumulator to reduce the total latency. The chip complexity is approximately 10 OOO transistors ...

In this paper a novel architecture of multiplier and accumulator (MAC) for high speed arithmetic is presented. The architecture adopts radix-4 modified booth algorithm (MBA) and hybrid carry save adder, in which the accumulator that has the largest delay in MAC was merged into Carry save adder (CSA) block. The performance of final adder block, which determines critical path of the architecture,...