Abstarct The work presents the newly deploying technology in semiconductor industry called silicon on insulator (SOI). Its two technology partially and fully depleted SOI and describe how these are different from conventional bulk MOS technology, advantages over bulk technology and floating body effect of PD/FD SOI technology, factors effecting floating body such as kink effects in PD SOI, para...

A current-mode output driver that supports SERDES applications is implemented using 0.13 μm Bulk and PD SOI CMOS technologies. Schematic simulation results confirm the enhanced performance of PD SOI for very high-speed interfaces. The PD SOI current-mode driver shows a 3 times lower data dependent jitter than the Bulk current-mode driver at the same 3.125 Gbps data rate of XAUI standard.

The authors report a 0.7V Manchester carry look-ahead circuit using partially depleted (PD) SOI CMOS dynamic threshold (DTMOS) techniques for low-voltage CMOS VLSI systems. Using an asymmetrical dynamic threshold pass-transistor technique with the PD-SOI DTMOS dynamic logic circuit, this 0.7V PD-SOI DTMOS Manchester carry look-ahead circuit has an improvement of 30% in propagation delay time co...

In this article, a novel concept is introduced to improve the radio frequency (RF) linearity of partially-depleted (PD) silicon-on-insulator (SOI) MOSFET circuits. The transition due to the non-zero body resistance (RBody) in output conductance of PD SOI devices leads to linearity degradation. A relation for RBody is defined to eliminate the transition and a method to obtain transition-free c...

In this paper, we propose an Active Body-biasing Controlled (ABC)-Bootstrap PTL (Pass-Transistor Logic) on PD-SOI for ultra low power design. Although simply lowering the supply voltage (VDD) causes a lack of driving power, our boosted voltage scheme employing a strong capacitive coupling with ABC-SOI improves a driving power and allows lower voltage operation. We also present an SOI-SRAM desig...

The proliferation of both Partially Depleted SiliconOn-Insulator (PD-SOI) technology and domino circuit styles has allowed for increases in circuit performance beyond that of scaling traditional bulk CMOS static circuits. However, interactions between dynamic circuit styles and PD-SOI complicate testing. This paper describes the issues of testing domino circuits fabricated in SOI technology and...

This paper reviews the basic circuit issues of silicon-on-insulator (SOI) technology for metal-oxide-semiconductor (CMOS) circuits. The superior features of SOI in low power, high speed, high device density and the effect of floating body particularly in partial depletion (PD) SOI device are addressed. Analog and RF circuits are considered and their performances are compared with those reported...

This paper presents a fast statistical static timing and leakage power analysis in Partially-Depleted Silicon-On-Insulator (PD-SOI) CMOS circuits in BSIMSOI3.2 100 nm technology. The proposed timing analysis considers floating body effect on the propagation delay for more accurate timing analysis in PD-SOI CMOS circuits. The accuracy of modeling the leakage power in PD-SOI CMOS circuits is impr...

The High-K Metal Gate (HKMG) technology has become the keystone to reduce gate leakage and enable the continuous scaling of transistors towards 32nm node and beyond. However, the reduction of gate leakage in 32nm HKMG PD (Partially Depleted)-SOI (Silicon-On-Insulator) CMOS (Complementary Metal–Oxide–Semiconductor) inevitably changes the modeling methods for gate current, floating body effect, a...