Bang-Bang clock and data recovery (BBCDR) circuits are hard nonlinear systems due to the nonlinearity introduced by the binary phase detector (BPD). The specification of the CDR frequency response is determined by jitter tolerance and jitter transfer. In this paper, jitter transfer and jitter tolerance of the second-order BBCDR are characterized by formulating the time domain waveforms. As a re...

Jitter is a key performance factor in high-speed digital transmission systems, such as synchronous optical networks/synchronous digital hierarchy (SONET/SDH), optical transport networks (OTN), and 10 Gigabit Ethernet (GigE). This paper outlines the differences between telecom and datacom jitter standards and describes the various jitter applications for compliance testing of 10G small form-fact...

Bang-Bang clock and data recovery (BBCDR) circuits are hard nonlinear systems due to the nonlinearity introduced by the binary phase detector (BPD). The specification of the CDR frequency response is determined by jitter tolerance and jitter transfer. In this paper, jitter transfer and jitter tolerance of the second-order BBCDR are characterized by formulating the time domain waveforms. As a re...

Problem Statement. Everyone will agree that a key issue in the design of multi-GHz interface devices is jitter performance. To characterize jitter performance, do you measure timing jitter or period jitter of the device? Should the Bit Error Rate performance of the device also be tested? Is there any way to shorten the overall test time? And as always, is there a way to reduce the test cost? Fu...

This paper presents a new jitter tolerance model that includes the effect of deterministic jitter in interconnects. First, it is shown by experiment that the deterministic jitter in a cable can significantly affect its jitter tolerance. Then, the new jitter tolerance model is verified with experimental data on cables of various lengths, using both PRBS and T11 test patterns.

An integrated 10-Gb/s clock and data recovery circuit incorporates a LC-tank voltage-controlled oscillator, a half-rate binary phase detector and charge pump. On the basis of R.C.Walker's second-order model, and in accordance with jitter tolerance and jitter transfer, the minimum stability factor are derived in a view to determine the value of Cz and Rz finally. After the circuit design is acco...

As CMOS technology has scaled, supply voltage have dropped, chip power consumption has increased, and clock frequency/data rates increase effects of jitter become critical and jitter budget get tighter. Knowing how to inject/isolate jitter components with the time convolution/correlation method will enhance designer ability to determine and locate the root causes so that one can then proceed to...

1. The new definitions of jitter In the last few years, more and more serial link standards adopted the concept of separating jitter into deterministic jitter (DJ), periodic jitter (PJ) and random jitter (RJ). The old concept of histogram based peak-to-peak jitter has been replaced by the concept of total jitter (TJ), which is associated with a certain bit-error-rate for the serial link (typica...

A blind-oversampling CDR tracks the high-frequency jitter of the input data stream, but is limited at low-frequencies by the size of its FIFO [1]. A phase-tracking CDR, on the other hand, tracks jitter at frequencies below f3dB of its loop filter, but performs poorly beyond this frequency [2]. In this paper, a semi-blind-oversampling technique is presented. The proposed technique produces a jit...

Jitter is a key performance factor in high-speed digital transmission systems, such as synchronous optical networks/synchronous digital hierarchy (SONET/SDH), optical transport networks (OTN), and 10 Gigabit Ethernet (GE). This paper outlines the differences between telecom and datacom jitter standards and describes the various jitter applications for compliance testing of 10 G small form-facto...