In this paper, we propose a new heterostructure dual material gate junctionless field-effect transistor (H-DMG-JLFET), with negative differential resistance (NDR) characteristic. The drain and channel material are silicon and source material is germanium. The gate electrode near the source is larger. A dual gate material technique is used to achieve upward band bending in order to access n-i-p-...

in this paper, a low voltage and low power (lv/lp) operational transconductance amplifier (ota) using fgmos (floating-gate mos) transistor is proposed. the relative tuning range of 50 is achieved in this ota while only consumes 40 µw with 1.0 v supply voltage in tsmc 0.18 µm cmos technology. the simulation results of the proposed ota show an open loop gain of 30.2 db and a unity gain frequency ...

A concise arrafytical expression for switch-induced error voltage on a switched capacitor is derived from the distributed MQSFET model. The result, however, can be interpreted in terms of a simple lumped equivalent circuit. With this expression we explore the dependence of the error voltage on process, switch turnoff rate, source resistance, and other circuit parameters. These results can be us...

We demonstrate the advantages of dual-gate polysilicon nanoribbon biosensors with a comprehensive evaluation of different measurement schemes for pH and protein sensing. In particular, we compare the detection of voltage and current changes when top- and bottom-gate bias is applied. Measurements of pH show that a large voltage shift of 491 mV pH(-1) is obtained in the subthreshold region when t...

In the depletion approximation for n-channel MOS structures we have neglected the electrons beneath the gate electrode when the gate voltage is less than the threshold voltage, VT. We said that it is only when the gate voltage is above threshold that they are significant, and that they are then the dominant negative charge under the gate. Furthermore, we say that above threshold all of the gate...

In this work, the design and analysis of new Level Shifter with Gate Driver for Li-Ion battery charger is proposed for high speed and low area in 180nm CMOS technology. The new proposed level shifter is used to raise the voltage level and significantly reduces transfer delay 1.3ns (transfer delay of conventional level shifter) to 0.15ns with the same input signal. Also, the level shifter with g...

DRIVING eGaN® FETS When considering gate drive requirements, the three most important parameters for eGaN FETs are (1) the maximum allowable gate voltage, (2) the gate threshold voltage, and (3) the “body diode” voltage drop. The maximum allowable gate-source voltage for an eGaN FET of 6 V is low in comparison with traditional silicon. Secondly, the gate threshold is also low compared to most p...

DriviNG eGaN® FETs When considering gate drive requirements, the three most important parameters for eGaN FETs are (1) the maximum allowable gate voltage, (2) the gate threshold voltage, and (3) the “body diode” voltage drop. The maximum allowable gate-source voltage for an eGaN FET of 6 V is low in comparison with traditional silicon. Secondly, the gate threshold is also low compared to most p...