In this letter a useful CMOS fully-differential buffer topology is presented. The proposed solution, performing the common mode feedback (CMFB) operation, shows a rail-to-rail characteristic, so it is particularly suitable for low-voltage (± 0.75V) low-power (<400 μW) applications. The simulated results have shown excellent general performance, evaluated in terms of suitable figures of merit (F...

In this paper a novel common mode separation technique for implementing fully differential current buffers is introduced.  Using the proposed method two high CMRR (Common Mode Rejection Ratio) and high PSRR (Power Supply Rejection Ratio) fully differential current buffers in BIPOLAR and CMOS technologies are implemented.   Simulation results by HSPICE using 0.18μm TSMC process for CMOS based st...

We present a Switched-Current (SI) fourth-order bandpass Σ∆ modulator IC prototype. It uses fully-differential circuits in 0.8μm CMOS technology to obtain a Dynamic Range (DR) larger than 55 dB at 2.5MHz center frequency with 30kHz bandwidth in accordance to the requirements of AM digital receivers. The prototype incorporates a single-ended to fullydifferential current-mode buffer for testing p...

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This paper presents a high CMRR and wideband current feedback Instrumentation Amplifier (IA). The proposed IA architecture consists of Fully Balanced Differential Difference Amplifier (FBDDA) and Differential Difference Amplifier (DDA) based on 2 generation current conveyor (CCII) with a buffer. From the simulation results evaluated by HSPICE, the proposed IA exhibits average CMRR was 109.3 dB ...

A high performance bulk-driven rail-to-rail fully differential buffer operating from ±0.3V supplies in 180 nm CMOS technology is reported. It has a differential–difference input stage and common mode feedback circuits implemented with no-tail, CMRR pseudo-differential cells. operates subthreshold, infinite impedance, low output impedance (1.4 k?), 86.77 dB DC open-loop gain, 172.91 kHz bandwidt...

A high-speed fully differential current switch is presented. The clock-feedthrough effect is reduced by Swing-Reduced Drivers and neutralized by dummy transistors. With the use of Swing-Reduced Drivers (SRD), less charges are required to be transferred to/from the gates of the switching transistors, and hence, the switching speed can be increased without significant output error. The SRDs also ...

this paper presents a novel fully differential (FD) ultra high common mode rejection ratio (CMRR) current operational amplifier (COA) with very low input impedance. Its FD structure that attenuates common mode signals over all stages grants ultra high CMRR and power supply rejection ratio (PSRR) that makes it suitable for mixed mode and accurate applications. Its performance is verified by HSPI...