In this paper, a method of low power analog testing is proposed. In spite of having Oscillation Based Built in Self-Test methodology (OBIST), a look up table based (LUT) low power testing approach has been proposed to find out the faulty circuit and also to sort out the particular fault location in the circuit. In this paper an operational amplifier, which is the basic building block in the ana...

The way address sequences and data patterns appear on the outside of a memory may differ from their internal appearance; this effect is referred to as scrambling, which has a large impact on the effectiveness of the used tests. This paper presents an analysis of address and data scrambling for memory chips, at the layout and at the electrical level. A method is presented to determine the data b...

Linked faults are very important for memory testing because they reduce the fault coverage of the tests. Their analysis has proven to be a source for new memory tests, characterized by an increased fault coverage for a given test time. This paper presents an analysis of linked faults, based on the concept of fault primitives, such that the whole space of linked faults is investigated, accounted...

Many reliability prediction techniques require an estimate for the number of residual faults. In this paper, a new theory is developed for using test coverage to estimate the number of residual faults. This theory is applied to a specific example with known faults and the results agree well with the theory. The theory is used to justify the use of linear extrapolation to estimate residual fault...

Simulations run on sample circuits show that extremely high detection of bridging faults is possible using modifications of psuedo-exhaustive test sets. Real chips often contain bridging faults, and this research shows that stuck-at test sets are not sufficient for detecting such faults. The modified pseudo-exhaustive test sets are easy to generate and require little, or no, fault simulation. r...

The test can be developed at the functional level of the circuit. Such an approach allows developing the test at the early stages of the design process in parallel with other activities of this process. The problem is to choose the right fault model because the implementation of the circuit is not available yet. The paper introduces three new fault models for synchronous sequential circuits: fu...

Memory testing commonly faces two issues: the characterization of detailed and realistic fault models, and the definition of time-efficient test algorithms able to detect them. Among the different types of algorithms proposed for testing Static Random Access Memories (SRAMs), march tests have proven to be faster, simpler and regularly structured. The continuous evolution of the memory technolog...

Different test sequence selection methods, namely, the Dmethod, C-method, W-method, T-method, U-method, Uvmethod and the Wp-method, are reviewed and analysed for their fault detection capabilities. We show that the C-method and the Uv-method do not provide complete fault coverage. These seven methods are formally analysed for their fault diagnosis capabilities under single fault assumption. Amo...

A structurally testable delay fault might become untestable in the functional mode of the circuit due to logic or timing constraints or both. Experimental data suggests that there could be a large difference in the number of structurally and functionally testable delay faults. However, this difference is usually calculated based only on logic constraints. It is unclear how this difference would...

This paper deals with the verification of efficiency of the novel on-chip OBIST (Oscillation Built-In Self Test) strategy by comparison the fault coverage in selected types of active analog integrated filters. Fault coverage obtained by OBIST approach was compared to fault coverage results obtained by the measurement and evaluation of filters’ selected parameters.