A fast low-power 1-bit full adder circuit suitable for nano-scale CMOS implementation is presented. Out of the three modules in a common full-adder circuit, we have replaced one with a new design, and optimized another one, all with the goal to reduce the static power consumption. The design has been simulated and evaluated using the 65 nm PTM models.

This paper presents a 372ps 64-bit adder using Fast Pull-up Logic (FPL) in 0.18 μm CMOS technology. Fast Pullup Logic is devised and applied to decrease pull-up time which is critical in domino-static adder. The implemented adder measures the worst case delay of 372ps. The adder has a modified tree architecture using Load Distribution Method and has 6 logic stages.

The FFT is commonly used essential tool in digital signal processing applications .The adders used in Conventional Fast Fourier transform(FFT) are no longer appropriate for the reason that of its degraded rapidity concert. There are many dissimilar kinds of fast adders such as Carry Select Adder, Carry Save Adder and Carry Look Ahead Adder have been used for Fast Fourier Transform. However, the...

The terahertz optical asymmetric demultiplexer (TOAD) or semiconductor amplifier (SOA)-assisted Sagnac switches have been used to construct an all-optical 4-bit carry skip adder. This design aims satisfy the high speed and accuracy requirements of modern ultrafast digital transmission. Using a combination multiplexer full adder, we describe When compared ripple adder look-ahead may be employed ...

Arithmetic and Logic Unit (ALU), core unit of a processor, when used for scientific computations, will spend more time in multiplications. For higher order multiplications, a huge number of adders are to be used to perform the partial product addition. Reducing delay in the multiplier reduces the overall computation time. Wallace multipliers perform in parallel, resulting in high speed. It uses...

On this Technical era the excessive velocity and low area of VLSI chip are veryvery crucial elements. Each day quantity of transistors and different active and passive elements are drastically developing on a VLSI chip. All of the processors of the gadgets adders and multipliers are playing an essential position. An adder is a pleasing element for the designing of fast multiplier. Ultimately he...

In this paper, a novel technique for multiplication is presented using Vedic multiplier. Vedic multiplier uses adders and hence making fast adder will increase the overall speed for multiplication. We have done comparative analysis for multiplication using different architectures of adder. For comparison we have taken Carry Select Adder (CSA), Square Root Carry Select Adder (SQRT-CSA). We have ...

In this paper we explore the test complexity of the adder function with respect to the robust path delay fault model. A lower bound of (n 2) for the cardi-nality of a complete test set for a combinational n-bit adder is proven. This result is valid for any adder design known until now. In addition we present a fast O(p n)-time adder that is fully robust path delay fault testable with a test set...

In digital VLSI systems binary addition is the most significance arithmetic function. To a great extent adders are used as DSP lattice filter where the ripple carry adders are substituted by the parallel prefix adder to reduce delay. The requirement of adder is that it is fast and it has area efficient and low power consumption. In this the parallel prefix adder is introduced as speculative Han...