A novel 32 bit RISC architecture is presented which is the basis of a powerful general purpose microprocessor and in parallel a 16/32 bit xed point DSP processor. This unifying of RISC and DSP was not achieved by simply using a microprocessor and DSP core, but a new concept for the implementation of DSP processors has been developed. With the architecture presented it has been proven that a DSP...

We present a novel approach to model inter-processor communication in multi-DSP systems. In most multi-DSP systems, inter-processor communication is realized by transferring data over point-to-point links with hardware FIFO bu ers. Direct memory access (DMA) is additionally used to concurrently transfer data to the FIFO bu ers and perform computation. Our model accounts for the limited size of ...

Unlike general-purpose processors, digital signal processors (DSP processors) are strongly application-dependent. To meet the needs for diverse applications, a wide variety of DSP processors based on different architectures ranging from the traditional to VLIW have been introduced to the market over the years. The functionality, performance, and cost of these processors vary over a wide range. ...

EISC (Extendable Instruction Set Computer) is a compressed code architecture developed for embedded applications. In this paper, we propose a DSP-enhanced embedded microprocessor based on the 32-bit EISC architecture. We present how we could exploit the special features, and how we could overcome the deficits, of the EISC architecture to accelerate DSP applications with a relatively low hardwar...

In this papel; we present an application-speciJic Digital Signal Processor (DSP) for third generation wireless communications. The processor architecture and instruction set of proposed DSP are specially designed for the WCDMA system, where the Viterbi decoding and complex arithmetic are enhanced. These key features make the proposed DSP consume much lower processor MIPS and therefore outperfor...