This paper discusses recent research on methods for estimating configuration parameters for the Matrix Comparator used for linking unstandardized or heterogeneously standardized references. The matrix comparator computes the aggregate similarity between the tokens (words) in a pair of references. The two most critical parameters for the matrix comparator for obtaining the best linking results a...

Design of low voltage double-tail Comparator with pre-amplifier and latching stage is reported in this paper. Design has specially concentrated on delay of both single tail comparator and double-tail comparator, which are called clocked regenerative comparator. Based on a new dynamic comparator is proposed, where the circuit of conventional double tail dynamic comparator is modified for low pow...

Nano Magnetic Logic (NML) has been attracting application in optical computing, nanodevice formation, and low power. In this paper nanoscale architecture such as the decoder, multiplexer, and comparator are implemented on perpendicular-nano magnetic logic (pNML) technology. All these architectures with the superiority of minimum complexity and minimum delay are pointed. The proposed architectur...

Quantum-dot Cellular Automata (QCA) is an emerging and promising technology that provides significant improvements over CMOS. Recently QCA has been advocated as an applicant for implementing reversible circuits. However QCA, like other Nanotechnologies, suffers from a high fault rate. The main purpose of this paper is to develop a fault tolerant model of QCA circuits by redundancy in hardware a...

Low power 8 bit GDI magnitude comparator is proposed in this paper which has an advantage of minimum power dissipation, reduced propagation delay and less number of transistors required as compare to conventional CMOS magnitude comparator. Proposed GDI magnitude comparator is designed at 100MHz frequency with 1.8 v supply voltage using 180nm technology using CADENCE VLSI EDA tools. The performa...