Nowadays, bulk of the designers prefer to outsource some parts of their design and fabrication process to the third-part companies due to the reliability problems, manufacturing cost and time-to-market limitations. In this situation, there are a lot of opportunities for malicious alterations by the off-shore companies. In this paper, we proposed a new placement algorithm that hinders the hardwa...

| In this paper we investigate reducing the power consumption of a synchronous digital system by minimizing the total power consumed by the clock signals. We construct activity-driven clock trees wherein sections of the clock tree are turned oo by gating the clock signals. Since gating the clock signal implies that additional control signals and gates are needed, there exists a trade-oo between...

In this paper, we investigate reducing the power consumption of a synchronous digital system by minimizing the total power consumed by the clock signals. We construct activity-driven clock trees wherein sections of the clock tree are turned off by gating the clock signals. Since gating the clock signal implies that additional control signals and gates are needed, there exists a tradeoff between...

Minimizing clock skew is important in the design of high performance VLSI systems. We present a general clock routing scheme that achieves very small clock skews while still using a reasonable amount of wirelength. Our routing solution is based on the construction of a binary tree using geometric matching. For cell-based designs, the total wirelength of our clock routing tree is on average with...

Genetic algorithm is an effective methodology for solving combinatorial optimization problems, and numerous researchers have undertaken efforts to many kinds of improvement of GAs in order to solve problems in computer science. The clock signal and clock skew become more and more important for the circuit performance in VLSI layout design. Since there are salient shortcomings in the conventiona...

Zero skew clock routing is an issue of increasing importance in the realm of VLSI design. As a result of the increasing speeds of on-chip clocks, zero skew clock tree construction has become critical for the correct operation of high performance VLSI circuits. In addition, in an effort to both reduce power consumption and the deformation of clock signals at synchronizing elements on a chip, a m...

In nanometer-scale VLSI physical design, clock tree becomes a major concern on determining the total performance of the chip. Both the clock skew and the PVT (process, voltage and temperature) variations contribute a lot to the behavior of the digital circuits. Previous works mainly focused on skew and wirelength minimization. However, it may lead to negative influence on the variation factors....

Minimizing clock skew is a very important problem in the design of high performance VLSI systems. We present a general clock routing scheme that achieves extremely small clock skews, while still using a reasonable amount of wire length. This routing solution is based on the construction of a binary tree using recursive geometric mat thing. We show that in the average case the total wire length ...

In this paper, we associate grey relational clustering with DME approach, called GDME, for solving the problem of clock tree construction. The experimental results show that our GDME improves up to 3.58% on total average in terms of total wire length than that of other DME algorithms. Additionally, our results of zero-skew RLC-based clock trees compared with Hspice are lower to 0.017% and 0.2% ...

Entitled: " Congestion Driven Clock Tree Routing with Via Minimization " and submitted in partial fulfillment of the requirements for the degree of Master of Applied Science Complies with the regulations of this University and meets the accepted standards with respect to originality and quality. Physical routability constraints such as legal location checking and excessive number of vias are us...