floorplanning is an important step in physical design of vlsi circuits. it is used to plan the positions of a set of circuit modules on a chip in order to optimize the circuit performance. however, modern floorplanning takes better care of providing extra options to place dedicated modules in the hierarchical designs to align circuit blocks one by one within certain bounding box for helping seq...

A broadband Circuit Analogue (CA) absorber using double-circular-loop array is investigated in this paper. A simple equivalent circuit model is presented to accurately analyze this CA absorber. The circuit simulation of the proposed model agrees well with full-wave simulations. Optimization based the equivalent circuit model, is applied to design a single-layer circuit analogue absorber using d...

A fast low-power 1-bit full adder circuit suitable for nano-scale CMOS implementation is presented. Out of the three modules in a common full-adder circuit, we have replaced one with a new design, and optimized another one, all with the goal to reduce the static power consumption. The design has been simulated and evaluated using the 65 nm PTM models.

quantum-dot cellular automata (qca) is an emerging and promising technology that provides significant improvements over cmos. recently qca has been advocated as an applicant for implementing reversible circuits. however qca, like other nanotechnologies, suffers from a high fault rate. the main purpose of this paper is to develop a fault tolerant model of qca circuits by redundancy in hardware a...

Design and construction of a capacitor sensor with a precise readout system are described in this paper. A variable air-gap capacitive transducer was constructed and for signalmeasurement a successful attempt was made to exploit the capacitance changes in terms of the phase angle of the detected signal. The reported setup makes it possible to detect capacitance changes of the order of 2.5 fF in...

This paper introduces a peculiar approach of designing Static Random Access Memory (SRAM) memory cell in Quantum-dot Cellular Automata (QCA) technique. The proposed design consists of one 3-input MG, one 5-input MG in addition to a (2×1) Multiplexer block utilizing the loop-based approach. The simulation results reveals the excellence of the proposed design. The proposed SRAM cell achieves 16% ...