نتایج جستجو برای: Carry Select Adder
تعداد نتایج: 145825 فیلتر نتایج به سال:
Abstract -This paper presents an architecture for a high-speed carry select adder with very long bit lengths utilizing a conflict-free bypass scheme. The proposed scheme has almost half the number of transistors and is faster than a conventional carry select adder. A comparative study is also made between the proposed adder and a Manchester carry chain adder which shows that the proposed scheme...
To perform fast addition operation, CSLA is one of the fastest adders used in many dataprocessing processors. There is further scope of improving the performance parameters of CSLA. This paper provides a comparative analysis of CSLA and reviews about various proposed schemes used to reduce the delay time, area occupied and power consumption in CSLA.
With the growing importance of electronic products in day-to-day life, the need for portable electronic products with low power consumption largely increases. In this paper, an area efficient high speed and low power Multiply Accumulator unit (MAC) with carry look-ahead adder (CLA) as final adder is being designed. In the same MAC architecture design in final adder stage of partial product unit...
This paper presents a novel approach for theoretical estimation of power consumption in digital binary adders. Closed-form expressions for power consumption of four different types of binary adders – the ripple-carry adder, the Manchester adder, a multiplexor-based carry-select adder and an efficient tree-based look-ahead adder – are derived in terms of word-length and pre-computed technologysp...
All reversible circuits have an intrinsic advantage over traditional irreversible circuits, because the reduce power consumption. Due to this, reversible circuits have been a source of constant excitement and great enthusiasm in the scientific community. Reversible logic is highly useful in nanotechnology, low power design and quantum computing. This paper proposes a design for a faster adder u...
This paper proposes an architecture for implementing a self-checking 4-bit carry select adder that can be extended to any n-bit addition. The overhead is directly proportional to the number of transistors in the adder.
A parallel adder which is optimal in both delay and size under left-to-right input arrival is proposed. The delay is the computation time after the arrival of the nal input bits. The proposed adder is composed of a carry select adder (CSA) and a small adder based on the on-they conversion (OTFA). Parallel computation in the CSA and the OTFA which make full use of the delay of the input arrival ...
A carry-select adder can be implemented by using single ripple carry adder and an add-one circuit [1] instead of using dual ripple-carry adders. This paper proposes a new add-one circuit using the first zero finding circuit and multiplexers to reduce the area and power with no speed penalty. For bit length n = 64, this new carry-select adder requires 38 percent fewer transistors than the dual r...
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