In the past Smart Power System-on-Chip (SoC) products were almost exclusively designed on Bipolar-CMOS-DMOS (BCD) technologies. These products address applications as diverse as power management for mobile phones, motor drivers, printer head drivers, automotive bus transceivers and dataline drivers for high speed internet or Voice over IP (VoIP). The trend towards SoC design for lowering form f...

In this paper we present a full characterization of HV CMOS transistors for a 20-120V CMOS technology including DC, AC and mismatch behavior. The model is based on a sub-circuit, which describes the geometry dependent AC and DC behavior of the device as well as the parasitic substrate currents and capacitance. The sub-circuit includes the correct description of the drain current and the parasit...

As the high-voltage (HV) and low-voltage (LV) circuits are integrated together in a common silicon substrate, parasitic latch-up path between neighboring HV LV with limited spacing layout would be triggered into state to cause unrecoverable failure chip. In this work, isolation ring of n-well (HVNW) / N-buried layer (NBL) Schottky-embedded junction overcome lateral HV-to-LV was proposed verifie...