This paper presents an investigation on the processes, trends, and applications of the BiCMOS technology in the fields of microelectronics and communication electronics. The investigation will focus on the design perspectives and different modifications that were developed to provide a very-high performance BiCMOS integrated circuit for both digital and mixed-signal applications. E. A. Gonzalez...

BiCMOS technology [1] offers both the high driving capability of bipolar devices and the high input impedance of CMOS devices. The potential of BiCMOS technology has been demonstrated in a variety of applications such as gate arrays [2], static RAMs [3], dynamic RAMs [4] and microprocessors [5]. One of drawbacks of the conventional BiCMOS process is that the integration density is rather low si...

New true-single-phase-clocking (TSPC) BiCMOS/ BiNMOS/BiPMOS dynamic logic circuits and BiCMOS/BiNMOS dynamic latch logic circuits for high-speed dynamic pipelined system applications are proposed and analyzed. In the proposed circuits, the bootstrapping technique is utilized to achieve fast near-full-swing operation. The circuit performance of the proposed new dynamic logic circuits and dynamic...

This paper describes submicron process technologies that allow a full implementation of CPU, first level Cache, second level Cache, and the main memory in a BiCMOS approach. CPU Standard Cells up to l00K ECL gate density with embedded CMOS and BiCMOS SRAM, X9 Cache memories, and 1 Meg ECL U0 SRAMs with less than 7ns access time are achieved. INTRODUCTION State-of-the-art BiCMOS technologies are...

In this paper the design of a new high-speed current mode BiCMOS logic circuits isproposed. By altering the threshold detector circuit of the conventional current mode logic circuitsand applying the multiple value logic (MVL) approach the number of transistors in basic logicoperators are significantly reduced and hence a reduction of chip area and power dissipation as wellas an increase in spee...

This paper examines the suitability of advanced SiGe BiCMOS and sub 65nm CMOS technologies for applications beyond 80GHz. System architectures are discussed along with the detailed comparison of VCOs, LNAs, PAs and static frequency dividers fabricated in CMOS and SiGe BiCMOS, as required for automotive cruise-control radar, high data-rate radio, and active and passive imaging in the 80GHz to 16...

This paper presents the design and performance comparison of a two stage operational amplifier topology using CMOS and BiCMOS technology. This conventional op amp circuit was designed by using RF model of BSIM3V3 in 0.6 μm CMOS technology and 0.35 μm BiCMOS technology. Both the op amp circuits were designed and simulated, analyzed and performance parameters are compared. The performance paramet...

System-level buses consume much more power by orders of magnitude than on-chip buses. Existing bus encoding schemes are based on rail-to-rail CMOS bus drivers while recent high-performance devices include BiCMOS bus drivers to achieve transfer bandwidth required. BiCMOS drivers consume significant quiescent power as well as active power proportional to the bus frequency. This paper introduces a...

This paper presents a 23–32 GHz wideband BiCMOS low-noise amplifier (LNA). The LNA utilizes coupled-resonators to provide a wideband load. To our knowledge, the proposed LNA achieves the widest bandwidth with minimum power consumption using 0.18 m BiCMOS technology in K-band. Analytical expressions for the wideband input matching, gain, noise figure and linearity are presented. The LNA is imple...

We investigate signal-to-noise ratio (SNR) characteristics of an 850-nm optoelectronic integrated circuit (OEIC) receiver fabricated with standard 0.25-µm SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. The OEIC receiver is composed of a Si avalanche photodetector (APD) and BiCMOS analog circuits including a transimpedance amplifier with DC-balanced buffer, a tunable e...