Low-power, compact, and highperformance NP dynamic CMOS circuits are presented in this paper assuming a 16 nm carbon nano tube transistor technology. The performances of two-stage pipeline 32-bit carry lookahead adders are evaluated based on HSPICE simulation with the following four different implementations: silicon MOSFET (Si-MOSFET) domino logic, Si-MOSFET NP dynamic CMOS, carbon nanotube MO...

A low cost design and simple to implement, CMOS NP Domino logic is presented. The NP Domino logic designs require fewer transistors and are compatible with full Domino logic. The performance of NP Domino logic is also better compared to the standard Domino logic implementations. Dynamic domino logic are very good but had many challenges like monotonicity, leakage, charge sharing and noise probl...

Quiescent power supply current monitoring (looa) has been shown to be effective for testing CMOS devices. BiCA4OS is emerging as a major technologv for high speed, high performance, digital and mixed signal applications. Stuck-ON faults as well as bridging faults in BiCMOS circuits cause enhanced IDDo. An input pattern classi$ation scheme is presented for detection of stuck-ONhridging faults ca...

This paper considers the fault detection problem for a single fault in a single MOS channel-connected subcircuit. We identify the following three decision sub-problems : (i) decide if a test vector exists; (ii) decide if an initializing vector exists; and (iii) decide if a test pair is robust. We prove that each of these problems is NP complete. More importantly, we prove that the rst two remai...

Data-Driven Dynamic Logic (D3L) is an appropriate candidate for replacing conventional dynamic logic in many cases. In our previous paper, we have shown how a D3L-based design can be used in place of a conventional Domino logic [l]. The designed circuit has been shown to have up to 30% less power dissipation compared to its Domino counterpart. This is in addition to the fact that no speed degra...