نتایج جستجو برای: حافظه dram

تعداد نتایج: 6485  

پایان نامه :وزارت علوم، تحقیقات و فناوری - دانشگاه علوم بهزیستی و توانبخشی 1379

هدف از این پژوهش، مقایسه کارکرد حافظه بیماران اسکیزوفرنیک با شروع در نوجوانی و بیماران اسکیزوفرنیک با شروع در بزرگسالی بود 60 یمار اسکیزوفرنیک، شامل 30 بیمار اسکیزوفرنیک با شروع در نوجوانی و 30 بیمار اسکیزوفرنیک با شروع در بزرگسالی، بصورت نمونه گیری قضاوتی (نظری)، از بین بیماران اسکیزوفرنیک بستری در بیمارستان های رازی شهر تهران و ملاصدرا شیراز انتخاب شدند. دو گروه مورد مقایسه از نر متغیرهایی چو...

Ahmad Munir Che Muhamed Albert Tan Yi Wey Ang Boon Suen Goh Kok Wei Rabindarjeet Singh,

Introduction: The objective of this study was to examine the influence of sahour meal on exercise performance, and physiological responses to a 10Km Time-Trial (10KTT) at two different times of the day during Ramadan. Method: Three well-trained Muslim runners participated (age, 25±0.8years; maximal oxygen uptake, 54.87±3.45 ml.kg-1.min-1; body weight, 52.4±1.99 kg; height, 162.7±3.55 cm).  Subj...

Journal: :CoRR 2016
Donghyuk Lee

In modern systems, DRAM-based main memory is significantly slower than the processor. Consequently, processors spend a long time waiting to access data from main memory, making the long main memory access latency one of the most critical bottlenecks to achieving high system performance. Unfortunately, the latency of DRAM has remained almost constant in the past decade. This is mainly because DR...

Journal: :CoRR 2017
Kevin K. Chang Abdullah Giray Yaglikçi Saugata Ghose Aditya Agrawal Niladrish Chatterjee Abhijith Kashyap Donghyuk Lee Mike O'Connor Hasan Hassan Onur Mutlu

The energy consumption of DRAM is a critical concern in modern computing systems. Improvements in manufacturing process technology have allowed DRAM vendors to lower the DRAM supply voltage conservatively, which reduces some of the DRAM energy consumption. We would like to reduce the DRAM supply voltage more aggressively, to further reduce energy. Aggressive supply voltage reduction requires a ...

2014
Prateek Asthana Sangeeta Mangesh

In this paper average power consumption of dram cell designs have been analyzed for the nanometer scale memories. Many modern processors use dram for on chip data and program memory. The major contributor of power in dram is the off state leakage current. Improving the power efficiency of a dram cell is critical for the improvement in average power consumption of the overall system. 3T dram cel...

2014
Ishan G Thakkar Sudeep Pasricha

In recent years, due to well-known “memory-wall” limitations, DRAM latency and energy/bit characteristics have not improved as rapidly as DRAM capacity and bandwidth with technology scaling. Despite plenty of research efforts during the last decade to overcome the hurdles in DRAM scaling, high performance computing systems of the future will still require improvements in DRAM latency and bandwi...

Journal: :CoRR 2017
Kevin K. Chang

Over the past two decades, the storage capacity and access bandwidth of main memory have improved tremendously, by 128x and 20x, respectively. These improvements are mainly due to the continuous technology scaling of DRAM (dynamic random-access memory), which has been used as the physical substrate for main memory. In stark contrast with capacity and bandwidth, DRAM latency has remained almost ...

Journal: :Cell cycle 2009
Jim O'Prey Joanna Skommer Simon Wilkinson Kevin M Ryan

Autophagy is a membrane-trafficking process that serves to deliver cytoplasmic proteins and organelles to the lysosome for degradation. The process is genetically defined and many of the factors involved are conserved from yeast to man. Recently, a number of new autophagy regulators have been defined, including the Damage-Regulated Autophagy Modulator (DRAM), which is a lysosomal protein that l...

2015
Yoongu Kim

For decades,mainmemory has enjoyed the continuous scaling of its physical substrate: DRAM(DynamicRandomAccessMemory). But now,DRAMscaling has reached a thresholdwhereDRAMcells cannot bemade smaller without jeopardizing their robustness. This thesis identifies two specific challenges to DRAM scaling, and presents architectural techniques to overcome them. First, DRAMcells are becoming less relia...

Journal: :CoRR 2016
Donghyuk Lee Yoongu Kim Gennady Pekhimenko Samira Manabi Khan Vivek Seshadri Kevin Kai-Wei Chang Onur Mutlu

This paper summarizes the idea of Adaptive-Latency DRAM (AL-DRAM), which was published in HPCA 2015 [64]. The key goal of AL-DRAM is to exploit the extra margin that is built into the DRAM timing parameters to reduce DRAM latency. The key observation is that the timing parameters are dictated by the worst-case temperatures and worst-case DRAM cells, both of which lead to small amount of charge ...

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