THE CURRENT TREND of SoC design has made conventional test methodologies increasingly difficult. Performing brute-force test pattern generation (ATPG) on the entire SoC is often infeasible, because the design can exceed the test pattern generator’s capabilities. At other times, some black-box third-party cores within the SoC might have their own test patterns generated at the core boundary. IEE...

With the adoption of the IEEE 1500 [1] Standard, the opportunity exists for System on Chip (SoC) designers to specify test systems in a generic way. As the IEEE 1500 Standard does not address the specification and design of the on-chip Test Access Mechanism (TAM), considerable effort may still be required if test engineers are to optimise testing SoCs with IEEE 1500 Wrapped Cores. This paper de...

With the adoption of the IEEE 1500 [1] Standard, the opportunity exists for System on Chip (SoC) designers to specify test systems in a generic way. As the IEEE 1500 Standard does not address the specification and design of the on-chip Test Access Mechanism (TAM), considerable effort may still be required if test engineers are to optimise testing SoCs with IEEE 1500 Wrapped Cores. This paper de...

THE INCREASED USE of embedded predesigned reusable cores necessitates a core-based test strategy, in which cores are tested as separate entities. The goal of IEEE Std 1500-2005 (Standard Testability Method for Embedded Core-Based Integrated Circuits) is to simplify reuse and facilitate interoperability for testing core-based system chips, especially if they contain cores from different sources....

SOC test methodology in ultra deep submicron (UDSM) technology with reasonable test time and cost has begun to satisfy high quality and reliability of the product. A novel hierarchical test architecture using IEEE standard 1149.1, 1149.7 and 1500 compliant facilities is proposed for the purpose of supporting flexible test environment to ensure SOC test methodology. Each embedded core in a syste...

Fortran 77 programs for the computation of modified Bessel functions of purely imaginary order are presented. The codes compute the functions Kia(x), Lia(x) and their derivatives for real a and positive x; these functions are independent solutions of the differential equation xw+xw+ (a−x)w = 0. The code also computes exponentially scaled functions. The range of computation is (x, a) ∈ (0, 1500]...

For system-on-chip (SoC) test based on IP cores integration reuse, the IEEE 1500 Standard has given specific testing architecture. In this paper, we aim at building controllable test architecture for IP cores on SoC based on IEEE 1500 Standard. The technique applied is referred to as test control switch which is configured to the Wrapper of IP cores. We design a switch control register (SCR) to...